HD61203U

8

Timing Generator Circuit

The timing generator circuit generates display timing and operating clock for the HD61202U. This circuit

is required when the HD61203U is used with the HD61202U. Connect terminal M/S to high level (master

mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from

HD61830. In this case connect the terminals FS, DS1, and DS2 to high level and M/S to low level (slave

mode).

Bidirectional Shift Register

A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from

DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the

bidirectional shift register, which is on the DL side, corresponds to X1 and the highest order bit on the DR

side corresponds to X64.

Liquid Crystal Display Driver Circuit

The combination of the data from the shift register with the M signal allows one of the four liquid crystal

display driver levels V1, V2, V5 and V6 to be transferred to the output terminals (Table 1).

Table 1

Output Levels

Data from the Shift

Register

M

Output Level

11

V2

01

V6

10

V1

00

V5