IDT72V261LA/72V271LA

3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9

23

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

WEN

PAF

RCLK

(3)

REN

4673 drw 19

1

2

12

D-(m+1) words

Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)

WCLK

WEN

PAE

RCLK

12

12

(4)

REN

4673 drw 20

WCLK

WEN

HF

RCLK

REN

4673 drw 21

[

+ 1

D-1

2

D/2 + 1 words in FIFO

[

+ 2

D-1

2

[

+ 1

D-1

2

Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

NOTES:

1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.

2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.

NOTES:

1. n = PAE offset.

2. For IDT Standard mode.

3. For FWFT mode.

5. PAE is asserted and updated on the rising edge of WCLK only.

NOTES:

1. m = PAF offset.

2. D = maximum FIFO depth.

In IDT Standard mode: D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.

In FWFT mode: D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.

4. PAF is asserted and updated on the rising edge of WCLK only.