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IDT72V2103 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72V2103 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 46 page  5 IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transitionofRCLK. IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode desiredisconfiguredduringmasterresetbythestateoftheProgrammableFlag Mode (PFM) pin. TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan once.ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit operation by setting the read pointer to the first location of the memory array. Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zero- latency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero-latency retransmit operation is selected the first data word to be retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK edgethatinitiatedtheretransmitbasedonRTbeingLOW. RefertoFigure11and12forRetransmitTimingwithnormallatency.Refer to Figure 13 and 14 for Retransmit Timing with zero-latency. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read outoftheFIFOinsmallword(x9)format.IfBig-Endianmodeisselected,then themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead IW OW Write Port Width Read Port Width L L x18 x18 L H x18 x9 H L x9 x18 H H x9 x9 TABLE 1 — BUS-MATCHING CONFIGURATION MODES outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis configured during master reset by the state of the Big-Endian (BE) pin. TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser to select the parity bit in the word loaded into the parallel port (D0-Dn) when programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then D8isassumedtobeavalidbitandD16andD17areignored.IPmodeisselected duringMasterResetbythestateoftheIPinputpin.Thismodeisrelevantonly when the input width is set to x18 mode. Interspersed Parity control only has aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe data written to and read from the FIFO. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and BoundaryScanArchitecture. If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol inputs)willimmediatelytakethedeviceoutofthepowerdownstate. TheIDT72V2103/72V2113arefabricatedusingIDT’shighspeedsubmi- cronCMOStechnology. |
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