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IDT72V3624 Datasheet(PDF) 14 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 14 Page - Integrated Device Technology |
14 / 34 page 14 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 1,024 x 36 x 2 occurs at time tSKEW1 or greater after the write. Otherwise, the subse- quent clock cycle can be the first synchronization cycle (see Figures 15, 16, 17, and 18). FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB) This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB) function is selected. In IDT Standard mode, the Full Flag (FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array. For both FWFT and IDT Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FlFO memory status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets the Full/Input Ready flag HIGH. ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat time tSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcycle can be the first synchronization cycle (see Figures 19, 20, 21, and 22). ALMOST-EMPTY FLAGS (AEA, AEB) TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads data from its array. The state machine that controls an Almost-Empty flag monitorsawritepointerandreadpointercomparatorthatindicateswhenthe FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2. Thealmost-emptystateisdefinedbythecontentsofregisterX1for AEBand register X2 for AEA. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost- Empty flag and Almost-Full flag offset programming section). An Almost- EmptyflagisLOWwhenitsFIFOcontainsXorlesswordsandisHIGHwhen itsFIFOcontains(X+1)ormorewords.AdatawordpresentintheFIFOoutput register has been read from memory. TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords remains LOW if two cycles of its synchronizing clock have not elapsed since thewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflagisset HIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization cycleifitoccursattimetSKEW2 orgreaterafterthewritethatfillstheFIFOto(X+1) words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst synchronization cycle. (See Figure 23 and 24). ALMOST-FULL FLAGS (AFA, AFB) TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors a write pointer and read pointer comparator that indicates when the FIFO memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FlFO reset, programmed from Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y) or (1,024-Y) for the IDT72V3624 or IDT72V3644 respec- tively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)] or [1,024-(Y+1)] for the IDT72V3624 or IDT72V3644 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [256/ 1,024-(Y+1)] or less words remains LOW if two cycles of its synchroniz- ing clock have not elapsed since the read that reduced the number of words in memory to [256/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [256/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [256/1,024-(Y+1)]. Otherwise, the subsequent synchro- nizing clock cycle may be the first synchronization cycle (see Figure 25 and 26). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control informationbetweenPortAandPortBwithoutputtingitinqueue.TheMailbox select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register employsdatalinesA0-A35.IftheselectedPortBbussizeis18bits,thenthe usable width of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then theusablewidthoftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase, A9-A35 are don’t care inputs.) A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of theMail2employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits, thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthis case, B18-B35 are don’t care inputs.) If the selected Port B bus size is 9 bits, thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B8.(Inthis case, B9-B35 are don’t care inputs.) Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2) LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW. Whendataoutputsofaportareactive,thedataonthebuscomesfromthe FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe mail register when the port Mailbox select input is HIGH. TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this case,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailboxdata are placed on B0-B8. (In this case, B9-B35 are indeterminate.) |
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