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CY7C408A-409A Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C408A-409A
Description  64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C408A-409A Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C408A
CY7C409A
11
If data is to be shifted out simultaneously with the data being
shifted in, the concept of “virtual capacity” is introduced. Virtual
capacity is simply how large a packet of data can be shifted in
at a fixed frequency, e.g., 35 MHz, simultaneously with data
being shifted out at any given frequency.
Figure 6 is a graph
of packet size[30] vs. shift out frequency (fSOx) for two different
values of shift in frequency (fSIx) when two FIFOs are
cascaded.
The exact complement of this occurs if the FIFOs initially con-
tain data and a high shift out frequency is to be maintained,
i.e., a 35 MHz fSOx can be sustained when reading data pack-
ets from devices cascaded two or three deep.[31] If data is
shifted in simultaneously,
Figure 6 applies with fSIx and fSOx
interchanged.
Figure 6. Virtual Capacity vs. Output Rate for Two FIFOs Cascaded Using an Inverter.
Notes:
30. These are typical packet sizes using an inverter whose delay is 4 ns.
31. Only devices with the same speed grade are specified to cascade together.
C408A–22
016
32 36
OUTPUT RATE(fSOx) OF BOTTOM FIFO (MHz)
0
150
50
400
300
412
20 24
8
28
100
200
250
fSIx =30MHz
350
fSIx =35MHz


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