ADuC845/ADuC847/ADuC848

Rev. B | Page 3 of 4

7. Level-Triggered Interrupt Operation [er007]

Background:

The ADuC845/ADuC847/ADuC848 incorporate two external interrupt sources (INT0 and INT1) that can be configured to

respond to either an edge event or a level event.

Issue:

If an interrupt occurs on the INT0 or INT1 pins and is then removed within one core instruction cycle, the interrupt vector

address that is generated may be incorrect, resulting in a vector to 0000H. This effectively restarts code execution.

Workaround:

To ensure that this does not occur, the level-triggered interrupt source must be kept low for a minimum of nine core clock

cycles.

Related Issues:

None.