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ADP1046AW Datasheet(PDF) 24 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
Download  88 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP1046AW Datasheet(HTML) 24 Page - Analog Devices

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ADP1046AW
Data Sheet
Rev. 0 | Page 24 of 88
VDD
When VDD is applied, a certain time elapses before the part is
capable of regulating the power supply. When VDD rises above
the power-on reset and UVLO levels, it takes approximately
20 μs for VCORE to reach its operational point of 2.5 V. The
EEPROM contents are then downloaded to the registers. The
download takes an additional 25 μs (approximately). After the
EEPROM download, the ADP1046AW is ready for operation.
If the ADP1046AW is programmed to power up at this time
(PSON is enabled), the soft start ramp begins. Otherwise, the
part waits for the PSON signal.
The proper amount of decoupling capacitance must be placed
between VDD and AGND, as close as possible to the device to
minimize the trace length. It is recommended that the VCORE
pin not be used as a reference or to generate other logic levels
using resistive dividers.
VDD/VCORE OVLO
The ADP1046AW has built-in overvoltage protection (OVP)
on its supply rails. When the VDD or VCORE voltage rises above
the OVLO threshold, the response can be programmed using
Register 0x0E[7:5]. It is recommended that when a VDD/VCORE
OVP fault occurs, the response be set to download the EEPROM
before restarting the part (set Register 0x0E[6] = 1).
POWER GOOD
The ADP1046AW has two open-drain power-good pins. The
PGOOD1 pin is driven low when a PGOOD1 fault condition
is present; the PGOOD2 pin is driven low when a PGOOD2
fault condition is present.
The PGOOD1 and PGOOD2 pins and flags can be programmed
to respond to the following flags:
Soft start
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
UVP
Local OVP (fast and accurate)
Load OVP
OrFET (GATE pin)
The masking of these flags is programmed in Register 0x7B
(for PGOOD1) and Register 0x7C (for PGOOD2). When a flag
is masked, it does not set PGOOD1 or PGOOD2.
The following additional flags can also set the PGOOD2 pin either
unconditionally or based on the flag response, as programmed
in Register 0x2D[3] (see Figure 31 and Table 45).
Voltage continuity
OrFET disable
ACSNS
External flag (FLAGIN pin)
OTP
These additional flags can be programmed in Register 0x2D[3]
to always set PGOOD2 or to set PGOOD2 only if the flag action
is not set to “ignore” in the fault configuration register for that
flag (see Table 12 and Table 13).
PGOOD1
(FLAG AND PIN)
PGOOD2
(FLAG AND PIN)
ADDITIONAL FLAGS
-VOLTAGE CONTINUITY
-OrFET DISABLE
-ACSNS
-FLAGIN
-OTP
MASKED BY
REG 0x7B
MASKED BY
REG 0x7C
DEBOUNCE
(REG 0x2D[7:6])
DEBOUNCE
(REG 0x2D[5:4])
MAIN FLAGS
-SOFT START
-CS1 FAST OCP
-CS1 ACCURATE OCP
-CS2 ACCURATE OCP
-UVP
-LOCAL OVP
(FAST AND ACCURATE)
-LOAD OVP
-OrFET (GATE PIN)
IF REG 0x2D[3] = 0, THE
ADDITIONAL FLAGS
ALWAYS AFFECT PGOOD2,
REGARDLESS OF THE
PROGRAMMED ACTION.
IF REG 0x2D[3] = 1, THE
ADDITIONAL FLAGS AFFECT
PGOOD2 ONLY IF THEY ARE
NOT SET TO BE IGNORED.
Figure 31. PGOOD1, PGOOD2 Programming


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