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ADP1046AW Datasheet(PDF) 22 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
Download  88 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP1046AW Datasheet(HTML) 22 Page - Analog Devices

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ADP1046AW
Data Sheet
Rev. 0 | Page 22 of 88
OrFET CONTROL (GATE PIN)
The GATE control signal drives an external OrFET. The OrFET
is used in redundant systems to protect against power flow into
the power supply from the output terminals of another supply.
This ensures that power flows only out of the power supply and
that the unit can be hot-swapped.
The GATE pin is a totem-pole output and does not require a
pull-up resistor. The GATE pin polarity can be programmed via
Register 0x2D[1] to be active high or active low. The GATE out-
put is CMOS level (0 V to 3.3 V). An external driver is required
to turn the OrFET on or off.
OrFET Turn-On
The turn-on process for the OrFET is controlled by the voltage
difference between VS1 and VS2. For this reason, the VS1 and
VS2 readings must be correctly calibrated for the OrFET func-
tion to perform properly.
The OrFET turn-on circuit detects the voltage difference between
VS1 and VS2 (see Figure 26). When the forward voltage drop from
VS1 to VS2 is greater than the programmable OrFET enable
threshold set in Register 0x30[6:5], the OrFET is enabled. The
OrFET enable threshold can be set to 0%, −0.5%, −1%, or −2%
of the nominal output voltage.
OrFET Turn-Off
The OrFET can be turned off by three methods:
Fault flag. Any flag in a fault configuration register
(Register 0x08 to Register 0x0D) can be programmed with
an action to turn off the OrFET. The OrFET is kept off for
as long as the flag is set.
OrFET programmable comparator. If the reverse voltage
present on CS2± exceeds the analog comparator threshold
programmed in Register 0x30[4:2], the OrFET is turned off.
This comparator can be disabled using Register 0x30[0].
GATE signal disable. When Register 0x5D[0] = 1, the
GATE signal is disabled and has no effect on the VSx
feedback point.
OrFET GATE Control and Regulation Points
The GATE signal is enabled when the threshold configured
in Register 0x30[6:5]) is met. The GATE signal controls a very
important function of output voltage regulation: the control
loop sensing point.
When the GATE signal is disabled, the OrFET is turned off
and the voltage regulation sensing point is VS1.
When the GATE signal is enabled, the OrFET is turned on
and the voltage regulation sensing point is VS3±.
Recommended Setup for a 12 V Application
In normal operating mode, follow this procedure:
When 12 V < VOUT < OVP, use the fast OrFET control
circuit to turn off the OrFET.
When VOUT > OVP, use load OVP to turn off the OrFET.
In light load mode, follow this procedure:
When 12 V < VOUT < OVP, use ACSNS to turn off the
OrFET.
When VOUT > OVP, use load OVP to turn off the OrFET.
In a 12 V application, when an internal short circuit occurs, use
CS1 OCP or VS1 UVP to shut down the unit and restart it.
FAST OrFET
COMPARATOR
FAST OrFET
THRESHOLD
OrFET
DISABLE
CS2–
CS2+
12V
11kΩ
11kΩ
1kΩ
1kΩ
VOUT
VS2
VS1
RSENSE
GATE
FAST OrFET
BYPASS
FAST OrFET
DEBOUNCE
S
R
Q
OrFET
ENABLE
OrFET
ENABLE THRESHOLD
FLAGS
DRIVER
DEBOUNCE
GATE
DISABLE
Figure 26. OrFET Control Circuit Detailed Internal Diagram


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