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ADP1046AW Datasheet(PDF) 74 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP1046AW Datasheet(HTML) 74 Page - Analog Devices

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ADP1046AW
Data Sheet
Rev. 0 | Page 74 of 88
Bits
Bit Name
R/W
Description
[2:0]
Slew rate
R/W
These bits specify the slew rate at the VS3± pins for the change in the voltage reference setting.
Bit 2
Bit 1
Bit 0
Slew Rate
0
0
0
200 mV/ms
0
0
1
100 mV/ms
0
1
0
50 mV/ms
0
1
1
25 mV/ms
1
0
0
12.5 mV/ms
1
0
1
6.25 mV/ms
1
1
0
3.125 mV/ms
1
1
1
1.5625 mV/ms (4 LSB/ms)
Table 96. Register 0x60—Normal Mode Digital Filter LF Gain Setting
Bits
Bit Name
R/W
Description
[7:0]
LF gain setting
R/W
This register determines the low frequency gain of the loop response in normal mode. The LF gain
is programmable over a 20 dB range (see Figure 58).
Table 97. Register 0x61—Normal Mode Digital Filter Zero Setting
Bits
Bit Name
R/W
Description
[7:0]
Zero setting
R/W
This register determines the position of the final zero in normal mode (see Figure 58).
Table 98. Register 0x62—Normal Mode Digital Filter Pole Setting
Bits
Bit Name
R/W
Description
[7:0]
Pole location
R/W
This register determines the position of the final pole in normal mode (see Figure 58).
Table 99. Register 0x63—Normal Mode Digital Filter HF Gain Setting
Bits
Bit Name
R/W
Description
[7:0]
HF gain setting
R/W
This register determines the high frequency gain of the loop response in normal mode. The HF
gain is programmable over a 20 dB range (see Figure 58).
Table 100. Register 0x64—Light Load Mode Digital Filter LF Gain Setting
Bits
Bit Name
R/W
Description
[7:0]
LF gain setting
R/W
This register determines the low frequency gain of the loop response in light load mode. The LF
gain is programmable over a 20 dB range (see Figure 58).
Table 101. Register 0x65—Light Load Mode Digital Filter Zero Setting
Bits
Bit Name
R/W
Description
[7:0]
Zero setting
R/W
This register determines the position of the final zero in light load mode (see Figure 58).
Table 102. Register 0x66—Light Load Mode Digital Filter Pole Setting
Bits
Bit Name
R/W
Description
[7:0]
Pole location
R/W
This register determines the position of the final pole in light load mode (see Figure 58).
Table 103. Register 0x67—Light Load Mode Digital Filter HF Gain Setting
Bits
Bit Name
R/W
Description
[7:0]
HF gain setting
R/W
This register determines the high frequency gain of the loop response in light load mode. The HF
gain is programmable over a 20 dB range (see Figure 58).
Table 104. Register 0x68—Reserved
Bits
Bit Name
R/W
Description
[7:0]
Reserved
R/W
Set these bits to 0x00 for proper operation.


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