Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADP1046AW Datasheet(PDF) 7 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
Download  88 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

ADP1046AW Datasheet(HTML) 7 Page - Analog Devices

Zoom Inzoom in Zoom Outzoom out
 7 / 88 page
background image
Data Sheet
ADP1046AW
Rev. 0 | Page 7 of 88
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Measurement Accuracy
Factory trimmed at 1 V
10 mV to 160 mV
−0.5
+0.5
% FSR
−8
+8
mV
0% to 100% of usable input voltage range
−3.0
+3.0
% FSR
−42
+42
mV
Temperature Readings Using
Internal Linearization Scheme
RTD source set to 46 µA (Register 0x11 set to
0xE6); NTC R0 = 100 kΩ, 1%; beta = 4250, 1%;
REXT = 16.5 kΩ, 1%
25°C to 100°C
7
°C
100°C to 125°C
5
°C
OTP
Threshold Accuracy
T = 85°C with 100 kΩ||16.5 kΩ
−0.25
+0.9
% FSR
−4
+14.4
mV
T = 100°C with 100 kΩ||16.5 kΩ
−0.5
+1.1
% FSR
−8
+17.6
mV
Comparator Speed
10.5
ms
OTP Threshold Hysteresis
16
mV
PGOOD1, PGOOD2, SHAREo PINS
Open-drain outputs
Output Low Voltage
VOL
0.4
V
PSON, SHAREi PINS
Digital inputs
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
VDD − 0.8
V
Leakage Current
1.0
µA
FLAGIN PIN
Digital input
Input Low Voltage
VIL
0.4
V
Input High Voltage
VIH
VDD − 0.8
V
Propagation Delay
Does not include debounce time (Register
0x0A[3] = 1); flag action set to disable PSU
200
ns
Leakage Current
1.0
µA
GATE PIN
Output Low Voltage
VOL
0.4
V
Output High Voltage
VOH
VDD − 0.4
V
SDA/SCL PINS
VDD = 3.3 V
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
VDD − 0.8
V
Output Low Voltage
VOL
0.4
V
Leakage Current
1.0
µA
SERIAL BUS TIMING
See Figure 2
Clock Operating Frequency
10
100
400
kHz
Bus-Free Time
tBUF
Between stop and start conditions
1.3
µs
Start Hold Time
tHD;STA
Hold time after (repeated) start condition;
after this period, the first clock is generated
0.6
µs
Start Setup Time
tSU;STA
Repeated start condition setup time
0.6
µs
Stop Setup Time
tSU;STO
0.6
µs
SDA Setup Time
tSU;DAT
100
ns
SDA Hold Time
tHD;DAT
For readback
125
ns
For write
300
ns
SCL Low Timeout
tTIMEOUT
25
35
ms
SCL Low Period
tLOW
1.3
µs
SCL High Period
tHIGH
0.6
µs
Clock Low Extend Time
tLO;SEXT
25
ms
SCL, SDA Fall Time
tF
20
300
ns
SCL, SDA Rise Time
tR
20
300
ns


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn