 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADP1046AW Datasheet(PDF) 68 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADP1046AW Datasheet(HTML) 68 Page - Analog Devices |
|
|
68 / 88 page 
ADP1046AW Data Sheet Rev. 0 | Page 68 of 88 Table 74. Register 0x4A—OUTC Rising Edge Setting (OUTC Pin) Bits Bit Name R/W Description [7:4] t5 R/W These bits contain the four LSBs of the 12-bit t5 time. This value is always used with the eight bits of Register 0x49, which contains the eight MSBs of the t5 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps. If the tRx and tFx of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the tRx and tFx occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t5 edge. 0 = no PWM modulation of the t5 edge. 2 t5 sign R/W 1 = negative sign. Increase of PWM modulation moves t5 right. 0 = positive sign. Increase of PWM modulation moves t5 left. 1 Reserved R/W Reserved. 0 Volt-second balance source selection R/W If this bit is set to 1, the OUTC rising edge is selected as the start of the integration period for volt-second balance. Table 75. Register 0x4B—OUTC Falling Edge Timing (OUTC Pin) Bits Bit Name R/W Description [7:0] t6 R/W This register contains the eight MSBs of the 12-bit t6 time. This value is always used with the top four bits of Register 0x4C, which contains the four LSBs of the t6 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps. If the tRx and tFx of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the tRx and tFx occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. Table 76. Register 0x4C—OUTC Falling Edge Setting (OUTC Pin) Bits Bit Name R/W Description [7:4] t6 R/W These bits contain the four LSBs of the 12-bit t6 time. This value is always used with the eight bits of Register 0x4B, which contains the eight MSBs of the t6 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps. If the tRx and tFx of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the tRx and tFx occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. 3 Modulate enable R/W 1 = PWM modulation acts on the t6 edge. 0 = no PWM modulation of the t6 edge. 2 t6 sign R/W 1 = negative sign. Increase of PWM modulation moves t6 right. 0 = positive sign. Increase of PWM modulation moves t6 left. [1:0] Reserved R/W Reserved. Table 77. Register 0x4D—OUTD Rising Edge Timing (OUTD Pin) Bits Bit Name R/W Description [7:0] t7 R/W This register contains the eight MSBs of the 12-bit t7 time. This value is always used with the top four bits of Register 0x4E, which contains the four LSBs of the t7 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps. If the tRx and tFx of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the tRx and tFx occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute maximum pulse width is tPERIOD − 5 ns. |
|
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
