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ADP1046AW Datasheet(PDF) 59 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP1046AW Datasheet(HTML) 59 Page - Analog Devices

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Data Sheet
ADP1046AW
Rev. 0 | Page 59 of 88
VOLTAGE SENSE REGISTERS
Table 49. Register 0x31—VS3 Voltage Setting (Remote Voltage)
Bits
Bit Name
R/W
Description
[7:0]
VS3 voltage setting
R/W
This register is used to set the output voltage (voltage differential at the VS3+ and VS3− pins). Each
LSB corresponds to a 0.6% increase. Setting this register to a value of 0xA0 gives an output voltage
setting of 100% of the nominal voltage. This is the default value that is stored in this register when
the part is shipped from the factory. Updating the VS3 voltage setting is a two-stage process. The
user must first change the value in this register; this information is stored in a shadow register. To
latch the new VS3 voltage setting into the state machine, the user must set the voltage reference
GO bit (Register 0x7F[0]). After that, the voltage changes with a limited slew rate (programmed in
Register 0x5F[2:0]).
Table 50. Register 0x32—VS1 Overvoltage Limit (OVP)
Bits
Bit Name
R/W
Description
[7:3]
VS1 OVP setting
R/W
Local overvoltage limit. This limit is programmable from 111.25% to 150% of the nominal VS1
voltage; 0x00 corresponds to 111.25%. Each LSB results in an increase of 1.25%. The VS1 OVP
threshold is calculated as follows:
VS1_OVP_Threshold = [(89 + VS1_OVP_Setting)/128] × 1.6 V
For example, if the VS1 OVP setting is 10, then
VS1_OVP_Threshold = [(89 + 10)/128] × 1.6 V = 1.2375 V
Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VS1 voltage.
Setting these bits to 7 gives an OVP limit of 120% of the nominal VS1 voltage.
Setting these bits to 15 gives an OVP limit of 130% of the nominal VS1 voltage.
Setting these bits to 31 gives an OVP limit of 150% of the nominal VS1 voltage.
2
Reserved
R/W
Reserved.
[1:0]
OVP sampling
R/W
The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP
threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using
these bits. If the number of samples is increased, the average voltage must be greater than the
OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average
voltage must be greater than the OVP threshold for both cycles.
Bit 1
Bit 0
Additional Sampling (μs)
0
0
0 (one sample sets the OVP flag)
0
1
80 (two samples set the OVP flag)
1
0
160 (three samples set the OVP flag)
1
1
240 (four samples set the OVP flag)
Table 51. Register 0x33—VS2 and VS3 Overvoltage Limit (OVP)
Bits
Bit Name
R/W
Description
[7:3]
VS2 and VS3
OVP setting
R/W
Local overvoltage limit. This limit is programmable from 111.25% to 150% of the nominal VSx
voltage; 0x00 corresponds to 111.25%. Each LSB results in an increase of 1.25%. The VSx OVP
threshold is calculated as follows:
VSx_OVP_Threshold = [(89 + VSx_OVP_Setting)/128] × 1.6 V
For example, if the VS2 OVP setting is 10, then
VS2_OVP_Threshold = [(89 + 10)/128] × 1.6 V = 1.2375 V
Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VSx voltage.
Setting these bits to 7 gives an OVP limit of 120% of the nominal VSx voltage.
Setting these bits to 15 gives an OVP limit of 130% of the nominal VSx voltage.
Setting these bits to 31 gives an OVP limit of 150% of the nominal VSx voltage.
2
Regulating point
R/W
When this bit is set, the ADP1046AW regulates from the VS3 node at all times. When this bit is not
set, the ADP1046AW uses the VS1 voltage as the regulating point during soft start and when the
OrFET is disabled.


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