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ADP1046AW Datasheet(PDF) 57 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
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Maker  AD [Analog Devices]
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ADP1046AW Datasheet(HTML) 57 Page - Analog Devices

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Data Sheet
ADP1046AW
Rev. 0 | Page 57 of 88
Bits
Bit Name
R/W
Description
2
Reserved
R/W
Set this bit to 0 for normal operation.
1
Disable light load
during soft start
R/W
0 = allow switching to light load mode filter during soft start.
1 = never switch to light load mode filter during soft start.
0
Force soft start
filter
R/W
0 = use normal mode filter or soft start filter, depending on the OrFET status. If regulating from
VS3 (OrFET on), the normal mode filter is used. If regulating from VS1 (OrFET off), the soft start
filter is used.
1 = use soft start filter as the initial filter regardless of OrFET status.
Table 45. Register 0x2D—PGOOD Debounce and Pin Polarity Settings
Bits
Bit Name
R/W
Description
[7:6]
PGOOD1 turn-on
debounce
R/W
These bits set the debounce time before the PGOOD1 pin and flag are set. This debounce time
starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD1 is always
immediate (no debounce).
Bit 7
Bit 6
Typical Debounce Time (ms)
0
0
350
0
1
150
1
0
550
1
1
0
[5:4]
PGOOD2 turn-on
debounce
R/W
These bits set the debounce time before the PGOOD2 pin and flag are set. This debounce time
starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD2 is always
immediate (no debounce).
Bit 5
Bit 4
Typical Debounce Time (ms)
0
0
350
0
1
150
1
0
550
1
1
0
3
PGOOD2 flags
R/W
The following flags can also set the PGOOD2 pin: voltage continuity, OrFET disable, ACSNS, FLAGIN,
and OTP. This bit specifies whether these flags unconditionally set PGOOD2 or whether these flags
set PGOOD2 only if the flag action is not set to ignore in the appropriate fault configuration register
(see Table 12 and Table 13).
0 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags always set the PGOOD2 pin.
1 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags set the PGOOD2 pin only if the
flag action is not set to ignore.
2
FLAGIN polarity
R/W
This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = 0 V = on).
1
GATE polarity
R/W
This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = 0 V = on).
0
PSON polarity
R/W
This bit sets the polarity of the PSON input pin: 1 = inverted (low = 0 V = on).
Table 46. Register 0x2E—Modulation Limit
Bits
Bit Name
R/W
Description
7
Full-bridge mode
R/W
Enable this bit when operating in full-bridge mode. It affects the modulation high limit.
[6:0]
Modulation limits
R/W
This value sets the minimum/maximum modulation limits relative to the nominal edge value. The
resolution depends on the switching frequency range.
Switching Frequency Range
Resolution Corresponding to LSB
48.8 kHz to 86.8 kHz
160 ns
97.7 kHz to 183.8 kHz
80 ns
195 kHz to 378.8 kHz
40 ns
390.6 kHz to 625.0 kHz
20 ns


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