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ADP1046AW Datasheet(PDF) 55 Page - Analog Devices

Part No. ADP1046AW
Description  Digital Controller for Isolated
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Maker  AD [Analog Devices]
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ADP1046AW Datasheet(HTML) 55 Page - Analog Devices

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Data Sheet
ADP1046AW
Rev. 0 | Page 55 of 88
Table 39. Register 0x27—CS1/CS2 Fast OCP Settings
Bits
Bit Name
R/W
Description
[7:6]
CS1 fast OCP debounce
R/W
These bits set the CS1 fast OCP debounce value. This is the minimum time that the CS1 signal
must be constantly above the fast OCP limit before the PWM outputs are shut down. When this
happens, all PWM outputs are disabled for the remainder of the switching cycle.
Bit 7
Bit 6
Debounce (ns)
0
0
0
0
1
40
1
0
80
1
1
120
5
CS2 nominal voltage
drop
R/W
These bits set the nominal full-scale voltage drop across the sense resistor. See the CS2 Trim
section for more information. These bits set the LSB step size of the CS2 ADC.
Bit 5
ADC Range (mV)
LSB Step Size (μV)
0
60
14.65
1
120
29.30
4
CS1 fast OCP bypass
R/W
Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin.
3
Constant current mode
R/W
When this bit is set, constant current mode is enabled to 97% of the CS2 accurate OCP limit.
1 = constant current mode enabled.
0 = constant current mode disabled.
2
CS2 current sensing
R/W
This bit is set high if high-side current sensing is used. This bit is set low if low-side current
sensing is used. See the CS2 Trim section for more information.
[1:0]
CS1 fast OCP timeout
R/W
If the CS1 fast OCP comparator is set, all PWM outputs that are on at that time are immediately
disabled for the remainder of the switching cycle. The PWM outputs resume normal operation at
the beginning of the next switching cycle. These bits set the number of consecutive switching
cycles for the comparator before the CS1 fast OCP response is activated.
Bit 1
Bit 0
Number of Switching Cycles
0
0
1
0
1
62
1
0
188
1
1
440
Table 40. Register 0x28—Volt-Second Balance Settings
Bits
Bit Name
R/W
Description
7
Reserved
R/W
Reserved.
6
Volt-second balance
enable
R/W
Setting this bit enables volt-second balance for the main transformer (used for full-bridge
configurations). For more information, see the Volt-Second Balance section.
5
Volt-second balance
leading edge blanking
R/W
Setting this bit means that CS1 is blanked for volt-second balance calculations at the rising
edge of the PWM outputs that are selected for volt-second balance. The blanking value is the
same value configured for CS1 fast OCP blanking in Register 0x22[7:5].
4
Volt-second disable
during soft start
R/W
0 = do not blank volt-second balance control during soft start.
1 = blank volt-second balance control during soft start.
3
50% blanking of each
phase
R/W
Setting this bit limits the sampling period for the current on CS1 to less than 50% of a half cycle.
2
Volt-second balance
modulation
R/W
This bit specifies the maximum amount of modulation from volt-second balance.
0 = ±80 ns maximum.
1 = ±160 ns maximum.
[1:0]
Volt-second balance
gain setting
R/W
These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of
64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.
When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.
Bit 1
Bit 0
Volt-Second Balance Gain
0
0
1
0
1
4
1
0
16
1
1
64


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