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NLSX4373MUTAG Datasheet(PDF) 9 Page - ON Semiconductor

Part No. NLSX4373MUTAG
Description  2-Bit 20 Mb/s Dual-Supply Level Translator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NLSX4373MUTAG Datasheet(HTML) 9 Page - ON Semiconductor

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Level Translator Architecture
The NLSX4373 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX4373 consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Each input/output channel has an internal 10 k
W pull.
The magnitude of the pullup resistors can be reduced by
connecting external resistors in parallel to the internal
10 k
W resistors.
Input Driver Requirements
The rise (tR) and fall (tF) timing parameters of the open
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (tPD), skew
(tPSKEW) and maximum data rate depend on the impedance
of the device that is connected to the translator. The timing
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 k
Enable Input (EN)
The NLSX4373 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the VL supply and has Overvoltage
Tolerant (OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage VL can be
greater than, less than or equal to VCC. The sequencing of
the power supplies will not damage the device during the
power up operation.
For optimal performance, 0.01
mF to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the voltage lines to the
ground plane of the PCB. The noise immunity will be
maximized by placing the capacitors as close as possible to
the supply and ground pins, along with minimizing the
PCB connection traces.

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