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MCP37210-200 Datasheet(PDF) 86 Page - Microchip Technology |
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MCP37210-200 Datasheet(HTML) 86 Page - Microchip Technology |
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86 / 116 page  MCP37210-200 AND MCP37D10-200 DS20005395B-page 86 2015-2016 Microchip Technology Inc. REGISTER 5-38: ADDRESS 0X80 – DIGITAL DOWN-CONVERTER CONTROL 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FCB<0> HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting. bit 6 HBFILTER_A: Select half-bandwidth filter at DDC output of channel A(1) 1 = Select High-Pass filter at DDC output 0 = Select Low-Pass filter at DDC output (Default) bit 5 EN_NCO: Enable NCO of DDC1 1 = Enabled 0 = Disabled (Default) bit 4 EN_AMPDITH: Enable amplitude dithering for NCO(2, 3) 1 = Enabled 0 = Disabled (Default) bit 3 EN_PHSDITH: Enable phase dithering for NCO(2, 3) 1 = Enabled 0 = Disabled (Default) bit 2 EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO 1 = Enabled 0 = Disabled (Default) bit 1 EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around fS/8/DER (4) 1 = Enabled 0 = Disabled (Default) bit 0 EN_DDC1: Enable digital down-converter 1 (DDC1) 1 = Enabled(5) 0 = Disabled (Default) Note 1: This filter includes a decimation of 2. 2: This requires the LFSR to be enabled: <EN_LFSR>=1 3: EN_AMPDITH = 1 and EN_PHSDITH = 1 are recommended for the best performance. 4: DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is disabled, output is I/Q data. 5: DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled together. REGISTER 5-39: ADDRESS 0X81 – DIGITAL DOWN-CONVERTER CONTROL 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FCB<5> EN_DDC2 GAIN_HBF_DDC FCB<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FCB<5>: Factory-Controlled bit. This is not for the user. Do not change default setting. bit 6 EN_DDC2: Enable DDC2 after the digital half-band filter (HBF) in DDC 1 = Enabled 0 = Disabled (Default) bit 5 GAIN_HBF_DDC: Gain select for the output of the digital half-band filter (HBF) in DDC 1 =x2 0 =x1 (Default) bit 4-0 FCB<4:0>: Factory-Controlled bits. This is not for the user. Do not change default settings. |
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