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TDP158 Datasheet(PDF) 36 Page - Texas Instruments

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Part No. TDP158
Description  6-Gbps, AC-Coupled to TMDS or HDMI Redriver
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TDP158 Datasheet(HTML) 36 Page - Texas Instruments

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TDP158
SLLSEX2 – DECEMBER 2016
www.ti.com
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Copyright © 2016, Texas Instruments Incorporated
8.5.10 CSR BIT FIELD DEFINITIONS, POWER MODE STATUS (address = 20h)
Figure 34. POWER MODE STATUS
7
6
5
4
3
2
1
0
Power Down
Status Bit
Standby Status
Bit
Loss of Signal
Status Bit –
LOS
Reserved
R/U
R/U
R/U
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. POWER MODE STATUS Field Descriptions
Bit
Field
Type
Reset
Description
7
Power Down Status Bit
R/U
1’b0
0 – Normal Operation
1 – Device in Power Down Mode.
6
Standby Status Bit
R/U
1’b0
0 – Normal Operation
1 – Device in Standby Mode
5
Loss of Signal Status Bit – LOS
R/U
1’b0
0 – Clock present
1 – No Clock present
4:0
Reserved
R
5’b00000
Reserved
8.5.11 CSR BIT FIELD DIFINITIONS, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
See Section 8.3.10 and 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to one
Figure 35. DP-Mode and INDIVIDUAL LANE CONTROL
7
6
5
4
3
2
1
0
Data Rate Select
Clock Lane
Lane D0
Lane D1
Lane D2
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Data Rate Select
R/W
2’b00
00 – 5.4 Gbps (default)
01 – 2.7 Gbps
10 – 1.62 Gbps
11 - Reserved
5
Clock Lane
R/W
1’b1
0 – Disabled
1 – Enabled (default)
4
Lane D0
R/W
1’b1
0 – Disabled
1 – Enabled (default)
3
Lane D1
R/W
1’b1
0 – Disabled
1 – Enabled (default)
2
Lane D2
R/W
1’b1
0 – Disabled
1 – Enabled (default)
1:0
Reserved
R
2’b00
Reserved


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