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SEC1210I-CN-02NC-TR Datasheet(PDF) 5 Page - Microchip Technology |
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SEC1210I-CN-02NC-TR Datasheet(HTML) 5 Page - Microchip Technology |
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5 / 218 page  2013 - 2016 Microchip Technology Inc. DS00001561C-page 5 SEC1110/SEC1210 •UART - Standard PC (9600, 19200, 38400 and 115200) baud rates supported - 3 M baud high-speed rate (non-PC standard) • SPI - Master capability with 12 MHz max performance • General - 5.0 V tolerance on user accessible IO pins - Self-clocking internal oscillator, no external crystal required - 3.6 V-5.5 V supply input - Internal 4.8 V comparator disables Class A card support if the input voltage is too low 1.2 Smart Card Subsystem The SEC1110 and SEC1210 are fully compliant with the prevailing Smart Card standards: ISO7816, EMV, and PC/SC. It meets and exceeds all existing requirements for communication bit rate (ETU duration) and includes support for pro- posed bit rates up to 826 Kbps. Signal levels and current limits are also fully compliant. The Smart Card power is regulated and switched internally, supporting all 5.0 V, 3.0 V, and 1.8 V Smart Cards (classes A, B, and C, respectively). Over-current protection is provided, and a detected over-current condition is available as an interrupt. The required standard activation and deactivation sequences are provided with software interaction. However, deactivation is handled in hardware as the card is being removed. This scenario ensures the required sequence regard- less of software participation. If the system clock is inactive at the time, the card movement is detected asynchronously, and the Wake-On Event feature is used to re-start the system clock so that the de-activation sequence can continue. Interface signals to the Smart Card are designed to meet both standard drive levels and current limitations internally, requiring no external series resistors. ESD protection on these signals meets the full standard requirements. The device is a superset of the familiar 16450 UART architecture, with extensions in the form of a larger FIFO, special- ized state machines for T=0 protocol parsing, automatic half-duplex turnaround at the completion of a transmitted mes- sage, and a specially-designed set of timers to enforce standards compliance in timing (as required of a terminal by the ISO7816 and EMV standards). With the full-packet-depth FIFO on-chip, software is almost totally excluded from real-time requirements. It loads an out- going message into the FIFO, triggers the transfer, and reads the returned data at any time after it becomes available. The reset sequence (cold or warm) is equally hands-off: software sets up the sequence and activates the reset, and is alerted when the ATR message has been received (via the FIFO Threshold Interrupt). The threshold is dynamically pro- grammable with byte granularity, so that threshold interrupts can be received at various stages in the processing of a message of initially unknown length (such as ATR). For detecting data time-outs, and for other mandatory timing tasks having to do with communication with a Smart Card, a set of three protocol timers is provided: • Time-out timer, for monitoring the standard WWT, BWT and WTX time-out intervals • CWT timer, for monitoring the T=1 CWT time-out interval • Guard timer, for ensuring the BGT and EGT transmission intervals, with special usage during a Reset sequence. A separate general purpose timer is provided for software driver use. Synchronous card support using GPIOs controlled via registers in the Smart Card device. |
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