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BT860-BT861 Datasheet(PDF) 57 Page - Synaptics Incorporated. |
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BT860-BT861 Datasheet(HTML) 57 Page - Synaptics Incorporated. |
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57 / 111 page  Bt860/861 3.0 Digital Processing and Functionality Multiport YCrCb to NTSC/PAL /SECAM 3.2 Effects D860DSA Conexant 3-27 3.2.15.3 General Teletext Operation A logical 1 on the TTXDAT pin corresponds to an analog output value of 66% of the black-to-white transition (approximately 462 mV above black), and a logical 0 corresponds to black. The Bt860/861 does not automatically provide any Teletext data, such as the clock run-in and framing code; the user must provide all data. Setting register bit TXE to 1 enables Teletext encoding. Register field TTXBF1[8:0] sets the start Teletext line for field 1, and register field TTXEF1[8:0] sets the end Teletext line for field 1. Register field TTXBF2 sets the start Teletext line for field 2, and register field TTXEF2[8:0] sets the end Teletext line for field 2. These 9-bit registers can be set to any value from 0–311, but setting the start line before line 7 is not recommended. The start line should be less than or equal to the end line. If the start and end lines for a field are the same value, Teletext is disabled for that field. Register bit SQUARE must be set to 0 for ITU-R BT.601 timing (27 MHz system clock), and 1 for square pixel timing (29 MHz system clock). The TTX_DIS register field allows the user to disable the Teletext function on specific lines in the odd and even fields as listed in Table 3-11. 3.2.16 Wide Screen Signaling Wide Screen Signaling (WSS) is used in 625-line systems on line 23. WSS data is 14 bits long and is entered on register bits WSS[14:1]. Register bits WSSDAT[20:15] are ignored. To enable WSS on field 1, line 23, set register bit EWSSF1 to 1. Register bit EWSSF2 is ignored, because WSS cannot be enabled on field 2. If the clock is at CCIR clock speeds (27 MHz), set register bit SQUARE to 0; if the clock is at square pixel speeds (29.5 MHz), set register bit SQUARE to 1. The clock run-in and start codes are automatically inserted onto the signal, but CRC data is not. Table 3-11. Teletext Line Disable Register Bit TTX Line (F1/F2) Register Bit TTX Line (F1/F2) TTX_DIS[0] 8 / 321 TTX_DIS[8] 16 / 329 TTX_DIS[1] 9 / 322 TTX_DIS[9] 17 / 330 TTX_DIS[2] 10 / 323 TTX_DIS[10] 18 / 331 TTX_DIS[3] 11 / 324 TTX_DIS[11] 19 / 332 TTX_DIS[4] 12 / 325 TTX_DIS[12] 20 / 333 TTX_DIS[5] 13 / 326 TTX_DIS[13] 21 / 334 TTX_DIS[6] 14 / 327 TTX_DIS[14] 22 / 335 TTX_DIS[7] 15 / 328 TTX_DIS[15] 23 / 336 |
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