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DSP56300FM Datasheet(PDF) 3 Page - Motorola, Inc |
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DSP56300FM Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 128 page Features Freescale Semiconductor PRELIMINARY 3 1.2 On-chip Memory Configuration • 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM. • 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM. • 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism. • 6Kx24 Bit Program RAM. • Various memory switches are available. See memory table below. 1.3 Peripheral modules • Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network and other programmable protocols. • Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network and other programmable protocols. Note: Available in the 80 pin package only • Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words. Three noise reduction filter modes. • Triple Timer module (TEC). • Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the 80 pin package and 20 pins on the 52 pin package. • Hardware Watchdog Timer 1.4 Packages • 80-pin and 52-pin plastic LQFP packages. Table 1. DSP56374 Memory Switch Configurations Bit Settings Memory Sizes (24-bit words) MSW1 MSW0 MS Prog RAM X Data RAM Y Data RAM Prog ROM X Data ROM Y Data ROM X X 0 6K 6K 6K 20K 4K 4K 0 0 1 2K 10K 6K 20K 4K 4K 0 1 1 4K 8K 6K 20K 4K 4K 1 0 1 8K 4K 6K 20K 4K 4K 1 1 1 10K 4K 4K 20K 4K 4K |
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