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DSP96002 Datasheet(PDF) 1 Page - Motorola, Inc

Part No. DSP96002
Description  32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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DSP96002 Datasheet(HTML) 1 Page - Motorola, Inc

 
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
DSP96002
Order this document by:
DSP96002/D, Rev. 2
©1996 MOTOROLA, INC.
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT
PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units
operating in parallel. The DSP96002 has two identical memory expansion ports with control
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which
facilitates easy interface with other processors for multiprocessor applications. Linear arrays
of DSP96002s can be implemented without glue logic. The MPU-style programming model
and instruction set allow straightforward generation of efficient, compact code. The high
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive
applications that require floating-point processing and access to large memory subsystems.
Figure 1 Block Diagram
Internal
Switch And Bit
Manipulation
Unit
Program Controller
Data
YAB
XAB
PAB
YDB
XDB
PDB
GDB
Program
Decode
Controller
Program
Address
Generator
Program
Interrupt
Controller
Clock
Generator
DDB
Dual Channel
DMA
Controller
Debug
Controller
4
Serial Debug
Port
MODB/IRQB
MODA/IRQA
RESET
External
Address
Switch
Address
Generation
Unit (AGU)
• IEEE Floating Point
• 32
× 32 Integer ALU
CLK
Memory
512
× 32
RAM
Memory
512
× 32
RAM
Program
1024
× 32
RAM and
64
× 32
Bootstrap
ROM
512
× 32†
ROM
512
× 32†
ROM
Data ALU
32-bit Buses
Address
External
Address
Switch
Bus
Control
Control
External
Data
Switch
Memory
X Data
Y Data
32
MODC/IRQC
Bus
Control
Control
Host
Interface
Data
32
*
**
*
*
*
*
Dual Access (DMA/Core)
4
4
18
18
Instruction
Cache
Timer
Timer
32
Address
32
1024
× 32 Virtual Locations
32-bit
Host
Interface
32-bit
OnCE
AA0306
Bus
External
Data
Switch
Bus
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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