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SST39VF6401B-70-4C-B1KE Datasheet(PDF) 9 Page - Microchip Technology |
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SST39VF6401B-70-4C-B1KE Datasheet(HTML) 9 Page - Microchip Technology |
9 / 36 page ©2015 DS20005008B 08/15 9 64 Mbit Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B Not Recommended for New Designs Data Protection The SST39VF640xB provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre- vents inadvertent writes during power-up or power-down. Hardware Block Protection The SST39VF6402B support top hardware block protection, which protects the top 32 KWord block of the device. The SST39VF6401B support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table 3. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase opera- tions on that block. Table 3: Boot Block Address Ranges Product Address Range Bottom Boot Block SST39VF6401B 000000H-007FFFH Top Boot Block SST39VF6402B 3F8000H-3FFFFFH T3.0 25008 |
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