EM47FM0888SBA

Write Leveling

For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control

signals, and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it

also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for

the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a

„write leveling‟ feature to allow the controller to compensate for skew.

Output Disable

The outputs may be enabled/disabled by MR1 (bit A12). When this feature is enabled (A12 = 1), all output pins

(DQs, DQS, /DQS, etc.) are disconnected from the device, thus removing any loading of the output drivers.

For normal operation, A12 should be set to

„0‟.

TQS, /TDQS

TDQS (Termination Data Strobe) provides additional termination resistance outputs that may be useful in some

system configurations. When enabled via the mode register, the same termination resistance function is applied

to the TDQS & /TDQS pins that is applied to the DQS & /DQS pins. In contrast to the RDQS function of DDR2

SDRAM, TDQS provides the termination resistance function only. The data strobe function of RDQS is not

provided by TDQS. The TDQS and DM functions share the same pin. When the TDQS function is enabled via

the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is

provided and the /TDQS pin is not used.

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