K9K1208U0M-YCB0, K9K1208U0M-YIB0

FLASH MEMORY

7

VALID BLOCK

NOTE :

1. The

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits

. Do not try

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

4,026

-

4,096

Blocks

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

-

200

500

µs

Number of Partial Program Cycles

in the Same Page

Main Array

Nop

-

-

2

cycles

Spare Array

-

-

3

cycles

Block Erase Time

-

2

3

ms

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

-

30

pF

Input Capacitance

-

30

pF

AC TEST CONDITION

(K9K1208U0M-YCB0 :TA=0 to 70

°C, K9K1208U0M-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)

Parameter

Value

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Times

5ns

Input and Output Timing Levels

1.5V

Output Load (3.0V +/-10%)

1 TTL GATE and CL=50pF

Output Load (3.3V +/-10%)

1 TTL GATE and CL=100pF

MODE SELECTION

2. WP should be biased to CMOS high or CMOS low for standby.

3. When GND input is high, spare area is deselected.

CLE

ALE

CE

WE

RE

GND

WP

Mode

H

L

L

H

X

X

Read Mode

Command Input

L

H

L

H

X

X

Address Input(4clock)

H

L

L

H

X

H

Write Mode

Command Input

L

H

L

H

X

H

Address Input(4clock)

L

L

L

H

H

Data Input

L

L

L

H

X

Sequential Read & Data Output

L

L

L

H

H

X

During Read(Busy)

X

X

X

X

X

H

During Program(Busy)

X

X

X

X

X

X

H

During Erase(Busy)

X

X

X

X

X

L

Write Protect

X

X

H

X

X