control logic

Soft

start

Thermal

Shtdwn

UVLO

PG control

power

control

error

amplifier

gate

drive

HS lim

LS lim

PVIN

PVIN

AVIN

PG

PGND

PGND

AGND

comp

comp

+

_

DCS - Control

TM

direct control

&

compensation

comparator

ramp

SW

SW

SW

EN

*

SS/TR

DEF

*

LOG

VOS

FB

(see Feature Description section).

Copyright © 2016, Texas Instruments Incorporated

8

TPS62130A-Q1, TPS62133A-Q1, TPS6213013A-Q1

SLVSCC2B – MAY 2014 – REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: TPS62130A-Q1 TPS62133A-Q1 TPS6213013A-Q1

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Copyright © 2014–2016, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The TPS6213xA-Q1 synchronous switched mode power converters are based on DCS-Control™ (Direct Control

with Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the

advantages of hysteretic, voltage mode and current mode control including an AC loop directly associated to the

output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast

comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and

provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback

loop is used. The internally compensated regulation network achieves fast and stable operation with small

external components and low ESR capacitors.

The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load

conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in

continuous conduction mode. This frequency is typically about 2.5 MHz with a controlled frequency variation

depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain

high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the

load current. Since DCS-Control™ supports both operation modes within one single building block, the transition

from PWM to Power Save Mode is seamless without effects on the output voltage.

9.2 Functional Block Diagram

Figure 7. TPS62130A-Q1 (Adjustable Output Voltage)