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ADS8681 Datasheet(PDF) 26 Page - Texas Instruments |
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ADS8681 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 74 page  Input Frequency (Hz) -15 -12 -9 -6 -3 0 3 10 100 1k 10k 100k D058 ±12.288 V ±10.24 V ±6.144 V ±5.12 V ±2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V Input Frequency (Hz) -135 -90 -45 0 45 10 100 1k 10k 100k D059 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 26 ADS8681, ADS8685, ADS8689 SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADS8681 ADS8685 ADS8689 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.3.4 Programmable Gain Amplifier (PGA) The device features a programmable gain amplifier (PGA) as part of the analog signal-conditioning circuit that converts the original single-ended input signal into a fully-differential signal to drive the internal SAR ADC. The PGA also adjusts the common-mode level of the input signal before feeding it into the SAR ADC to ensure maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be adjusted by setting the RANGE_SEL[3:0] bits in the configuration register (see the RANGE_SEL_REG register). The default or power-on state for the RANGE_SEL[3:0] bits is 0000, corresponding to an input signal range of ±3 × VREF. Table 3 lists the various configurations of the RANGE_SEL[3:0] bits for the different analog input voltage ranges. The PGA uses a precisely-matched network of resistors for multiple gain configurations. Matching between these resistors is accurately trimmed to keep the overall gain error low across all input ranges. Table 3. Input Range Selection Bits Configuration ANALOG INPUT RANGE RANGE_SEL[3:0] BIT 3 BIT 2 BIT 1 BIT 0 ±3 × VREF 0 0 0 0 ±2.5 × VREF 0 0 0 1 ±1.5 × VREF 0 0 1 0 ±1.25 × VREF 0 0 1 1 ±0.625 × VREF 0 1 0 0 0–3 × VREF 1 0 0 0 0–2.5 × VREF 1 0 0 1 0–1.5 × VREF 1 0 1 0 0–1.25 × VREF 1 0 1 1 7.3.5 Second-Order, Low-Pass Filter (LPF) In order to mitigate the noise of the front-end amplifier and gain resistors of the PGA, the AFE circuit of the device features a second-order, antialiasing LPF at the output of the PGA. The magnitude and phase response of the analog antialiasing filter are shown in Figure 51 and Figure 52, respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to 15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC. Figure 51. Second-Order LPF Magnitude Response Figure 52. Second-Order LPF Phase Response |
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