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ADS8671 Datasheet(PDF) 59 Page - Texas Instruments
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ADS8671 Datasheet(HTML) 59 Page - Texas Instruments
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SBAS779 – DECEMBER 2016
Product Folder Links: ADS8671 ADS8675
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Copyright © 2016, Texas Instruments Incorporated
Power Saving (continued)
9.2.2 Power-Down (PD) Mode
The device also features a deep power-down mode (PD) to reduce the power consumption at very low
The following steps must be taken to enter PD mode:
1. Write 69h to register address 05h to unlock the RST_PWRCTL_REG register.
2. Set the PWRDN bit in the RST_PWRCTL_REG register to 1b. The device enters PD mode on the rising
edge of the CONVST/CS signal.
In PD mode, all analog blocks within the device are powered down; however, the interface remains active and
the register contents are also retained. The RVS pin is high, indicating that the device is ready to receive the
In order to exit PD mode:
1. Clear the PWRDN bit in the RST_PWRCTL_REG register to 0b.
2. The RVS pin goes high, indicating that the device has started coming out of PD mode. However, the host
controller must wait for the t
time (see the Timing Requirements: Asynchronous Reset table) to elapse
before initiating a new conversion.
10.1 Layout Guidelines
Figure 99 illustrates a PCB layout example for the ADS867x.
Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the lower
side of the board and the digital connections are routed on the top side of the board.
Using a single dedicated ground plane is strongly encouraged.
Power sources to the ADS867x must be clean and well-bypassed. Using a 1-μF, X7R-grade, 0603-size
ceramic capacitor with at least a 10-V rating in close proximity to the analog (AVDD) supply pins is
recommended. For decoupling the digital supply pin (DVDD), a 1-μF, X7R-grade, 0603-size ceramic capacitor
with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the bypass
capacitors must be avoided. All ground pins must be connected to the ground plane using short, low-
There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, 0603-size ceramic
capacitor placed close to the device pins for decoupling the high-frequency signals and the second is a
10-μF, 0805-size ceramic capacitor to provide the charge required by the reference circuit of the device. A
capacitor with an ESR less than 0.2 Ω is recommended for the 10-μF capacitor. Both of these capacitors
must be directly connected to the device pins without any vias between the pins and capacitors.
The REFIO pin also must be decoupled with a minimum of 4.7-μF ceramic capacitor if the internal reference
of the device is used. The capacitor must be placed close to the device pins.
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