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ADS8671 Datasheet(PDF) 58 Page - Texas Instruments |
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ADS8671 Datasheet(HTML) 58 Page - Texas Instruments |
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58 / 72 page  Input Frequency (Hz) -80 -70 -60 -50 -40 -30 100 1k 10k 100k D057 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V Input Frequency (Hz) -100 -90 -80 -70 -60 -50 100 1k 10k 100k D056 ± 12.288 V ± 10.24 V ± 6.144 V ± 5.12 V ± 2.56 V 0-12.288 V 0-10.24 V 0-6.144 V 0-5.12 V 58 ADS8671, ADS8675 SBAS779 – DECEMBER 2016 www.ti.com Product Folder Links: ADS8671 ADS8675 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 9 Power Supply Recommendations The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on AVDD and DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the permissible range. 9.1 Power Supply Decoupling The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR) performance of the device. Figure 97 shows the PSRR of the device without using a decoupling capacitor. The PSRR improves when the decoupling capacitors are used, as shown in Figure 98. Figure 97. PSRR Without a Decoupling Capacitor Figure 98. PSRR With a Decoupling Capacitor 9.2 Power Saving In normal mode of operation, the device does not power down between conversions, and therefore achieves high throughput.However, the device offers two programmable low-power modes: NAP and power-down (PD) to reduce power consumption when the device is operated at lower throughput rates. 9.2.1 NAP Mode In NAP mode, the internal blocks of the device are placed into a low-power mode to reduce the overall power consumption of the device in the ACQ state. To enable NAP mode: • Write 69h to register address 05h to unlock the RST_PWRCTL_REG register. • The NAP_EN bit in the RST_PWRCTL_REG register must be set to 1b. The CONVST/CS pin must be kept high at the end of the conversion process. The device then enters NAP mode at the end of conversion and remains in NAP mode as long as the CONVST/CS pin is held high. A falling edge on the CONVST/CS brings the device out of NAP mode; however, the host controller can initiate a new conversion (CONVST/CS rising edge) only after the tNAP_WKUP time has elapsed (see the Timing Requirements: Asynchronous Reset table). |
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Similar Description - ADS8671 |
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