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ADC32RF80 Datasheet(PDF) 33 Page - Texas Instruments |
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ADC32RF80 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 136 page  Input Clock Divider (Divide-by-4) ASSERT SYSREF REG (In Master Page) SEL SYSREF REG (In Master Page) 0 1 CLKIN (CLKP-CLKM) SYSREF (SYSREFP-SYSREFM) DLL NCO, JESD Interface (LMFC Counter) MASK CLKDIV SYSREF (In JESD Digital Page) MASK NCO SYSREF (In JESD Digital Page) PDN SYSREF (In Master Page) 33 ADC32RF80, ADC32RF83 www.ti.com SBAS774A – MAY 2016 – REVISED DECEMBER 2016 Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Feature Description (continued) 8.3.3.1 Using SYSREF The ADC32RF8x uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 90. Figure 90. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter The ADC32RF8x samples the SYSREF signal on the input clock rising edge. Required setup and hold time are listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted, whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after disregarding the first two assertions, as shown in Table 1. Table 1. Asserting SYSREF SYSREF ASSERTION INDEX ACTION INPUT CLOCK DIVIDER NCO PHASE LMFC COUNTER 1 Gets reset Does not get reset Does not get reset 2 Gets reset Does not get reset Does not get reset 3 Gets reset Gets reset Gets reset 4 and onwards Gets reset Gets reset Gets reset |
Similar Part No. - ADC32RF80_16 |
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Similar Description - ADC32RF80_16 |
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