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74ALVC574 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74ALVC574
Description  Octal D-type flip-flop positive edge-trigger 3-state
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74ALVC574 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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2002 Mar 04
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
74ALVC574
FEATURES
• Wide supply voltage range from 1.65 to 3.6 V
• Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
• 3.6 V tolerant inputs/outputs
• CMOS low power consumption
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
• Latch-up performance exceeds ≤250 mA
• ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
DESCRIPTION
The 74ALVC574 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC574 is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) input
and an output enable (OE) input are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is
available at the outputs. When OE is HIGH, the outputs go
to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘374’, but the ‘374’
has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay CP to Qn
VCC = 1.8 V; CL = 30 pF; RL =1kΩ
3.1
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
2.3
ns
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
2.5
ns
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
2.5
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer
VCC = 3.3 V; notes 1 and 2
outputs enabled
21
pF
outputs disabled
13
pF


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