LAN91C100-FD-SS datasheet(3/77 Pages) SMSC

Part #	LAN91C100-FD-SS

Description	FEAST Fast Ethernet Controller with Full Duplex Capability

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Manufacturer	SMSC [SMSC Corporation]

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FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC LAN91C100FD Rev. D

Page 3

Revision 1.0 (09-22-08)

DATASHEET

Table Of Contents

Chapter 1

General Description .............................................................................................................5

Chapter 2

Pin Configuration................................................................................................................. 6

Chapter 3

Description of Pin Functions ............................................................................................... 7

Chapter 4

Functional Description....................................................................................................... 15

4.1

Description of Block........................................................................................................................... 15

4.1.1

Clock Generator Block............................................................................................................................15

4.2

CSMA/CD BLOCK............................................................................................................................. 15

4.2.1

DMA Block ..............................................................................................................................................15

4.2.2

Arbiter Block ...........................................................................................................................................15

4.2.3

MMU Block .............................................................................................................................................16

4.2.4

BIU Block ................................................................................................................................................16

4.2.5

MAC-PHY Interface Block ......................................................................................................................16

4.2.6

MII Management Interface Block ............................................................................................................17

4.2.7

Serial EEPROM Interface .......................................................................................................................17

Chapter 5

Data Structures and Registers .......................................................................................... 19

5.1

Packet Format in Buffer Memory ...................................................................................................... 19

5.2

Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 41

5.3

Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 42

5.4

Typical Flow of Events for Receive ................................................................................................... 43

5.5

Memory Partitioning .......................................................................................................................... 48

5.6

Interrupt Generation .......................................................................................................................... 49

Chapter 6

Board Setup Information .................................................................................................. 52

Chapter 7

Application Considerations ............................................................................................... 55

7.1

Fast Ethernet Slave Adapter ............................................................................................................. 55

7.2

VL Local Bus 32 Bit Systems ............................................................................................................ 55

7.3

High End ISA or Non-Burst EISA Machines...................................................................................... 58

7.4

EISA 32 Bit SLAVEEISA 32 Bit Slave............................................................................................... 60

Chapter 8

Operational Description .................................................................................................... 63

8.1

Maximum Guaranteed Ratings* ........................................................................................................ 63

8.2

DC Electrical Characteristics............................................................................................................. 63

Chapter 9

Timing Diagrams................................................................................................................ 66

Chapter 10

Package Outlines............................................................................................................. 76

List of Figures

Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13

Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14

Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18

Figure 5.1 - Data Packet Format ..................................................................................................................................19

Figure 5.2 - Interrupt Structure .....................................................................................................................................37

Figure 5.3 - Interrupt Service Routine ..........................................................................................................................44

Figure 5.4 - RX INTR ...................................................................................................................................................45

Figure 5.5 - TX INTR....................................................................................................................................................46

Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................47

Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................48

Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................51

Figure 6.1 - 64 X 16 Serial EEPROM Map ...................................................................................................................54

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