LAN9215 datasheet(42/144 Pages) SMSC

Part #	LAN9215

Description	16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

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Manufacturer	SMSC [SMSC Corporation]

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16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

42

SMSC LAN9215

DATASHEET

Note 3.10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the

setting of PME_EN.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the

LAN9215 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host

is required to check the READY bit and verify that it is set before attempting any other reads or writes

of the device. Before the LAN9215 is fully awake from this state the EDPWRDOWN bit in register 17

of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit

until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9215 is ready to resume

normal operation. At this time the WUPS field can be cleared.

Table 3.9 Power Management States

Device

BLOCK

D0

(NORMAL OPERATION)

D1

(WOL)

D2

(ENERGY DETECT)

PHY

Full ON

Energy Detect Power-Down

MAC Power

Management

Full ON

RX Power Mgmt. Block

On

OFF

MAC and Host

Interface

Full ON

OFF

Internal Clock

Full ON

OFF

KEY

CLOCK ON

BLOCK DISABLED – CLOCK ON

FULL OFF

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LAN9215 Datasheet(PDF) 42 Page - SMSC Corporation

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