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LAN9215I Datasheet(PDF) 55 Page - SMSC Corporation |
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LAN9215I Datasheet(HTML) 55 Page - SMSC Corporation |
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55 / 139 page  16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet SMSC LAN9215i 55 Revision 2.9 (03-01-12) DATASHEET 3.12.7 Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: If the actual packet length count does not match the Packet Length field as defined in the TX command. Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not match, the Ethernet controller will assert the Transmitter Error (TXE) flag. Host overrun of the TX data FIFO. Overrun of the TX status FIFO (unless TXSAO is enabled) 3.12.8 Stopping and Starting the Transmitter To halt the transmitter, the host must set the TX_STOP bit in the TX_CFG register. The transmitter will finish sending the current frame (if there is a frame transmission in progress). When the transmitter has received the TX status for this frame, it will clear the TX_STOP and TX_ON bits, and will pulse the TXSTOP_INT. Once stopped, the host can optionally clear the TX status and TX data FIFOs. The host must re-enable the transmitter by setting the TX_ON bit. If the there are frames pending in the TX data FIFO (i.e., TX data FIFO was not purged), the transmission will resume with this data. 3.13 RX Data Path Operation When an Ethernet Packet is received, the MIL first begins to transfer the RX data. This data is loaded into the RX data FIFO. The RX data FIFO pointers are updated as data is written into the FIFO. The last transfer from the MIL is the RX status word. The LAN9215i implements a separate FIFO for the RX status words. The total available RX data and status queued in the RX FIFO can be read from the RX_FIFO_INF register. The host may read any number of available RX status words before reading the RX data FIFO. The host must use caution when reading the RX data and status. The host must never read more data than what is available in the FIFOs. If this is attempted an underrun condition will occur. If this error occurs, the Ethernet controller will assert the Receiver Error (RXE) interrupt. If an underrun condition occurs, a soft reset is required to regain host synchronization. A configurable beginning offset is supported in the LAN9215i. The RX data Offset field in the RX_CFG register controls the number of bytes that the beginning of the RX data buffer is shifted. The host can set an offset from 0-31 bytes. The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9215i can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9215i is operating in a system that always performs multi-DWORD bursts. In such cases the LAN9215i must guarantee that it can transfer data in multiples of the Burst length regardless of the actual packet length. When configured to do so, the LAN9215i will add extra data at the end of the packet to allow the host to perform the necessary number of reads so that the Burst length is not cut short. Once a packet has been padded by the H/W, it is the responsibility of the host to interrogate the Packet length field in the RX status and determine how much padding to discard at the end of the Packet. It is possible to read multiple packets out of the RX data FIFO in one continuous stream. It should be noted that the programmed Offset and Padding will be added to each individual packet in the stream, since packet boundaries are maintained. |
Similar Part No. - LAN9215I_12 |
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Similar Description - LAN9215I_12 |
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