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LAN8700C-AEZG Datasheet(PDF) 8 Page - Microchip Technology |
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LAN8700C-AEZG Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 74 page  LAN8700/LAN8700i DS00002260A-page 8 2007-2016 Microchip Technology Inc. 3.0 PIN DESCRIPTION This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low. 3.1 I/O Signals The following buffer types are shown in the TYPE column of the tables in this chapter. • I Input. Digital LVCMOS levels. • IPD Input with internal pull-down. Digital LVCMOS levels. • O Output. Digital LVCMOS levels. • OPD Output with internal pull-down. Digital LVCMOS levels. • I/O Input or Output. Digital LVCMOS levels. • IOPD Input or Output with internal pull-down. Digital LVCMOS levels. • IOPU Input or Output with internal pull-up. Digital LVCMOS levels. • AI Input. Analog levels. • AO Output. Analog levels. Note: The digital signals are not 5V tolerant.They are variable voltage from +1.6V to +3.6V. TABLE 3-1: MII SIGNALS Signal Name Type Description TXD0 I Transmit Data 0: Bit 0 of the 4 data bits that are accepted by the PHY for transmission. TXD1 I Transmit Data 1: Bit 1 of the 4 data bits that are accepted by the PHY for transmission. TXD2 I Transmit Data 2: Bit 2 of the 4 data bits that are accepted by the PHY for transmission Note: This signal should be grounded in RMII Mode. TXD3 I Transmit Data 3: Bit 3 of the 4 data bits that are accepted by the PHY for transmission. Note: This signal should be grounded in RMII Mode nINT/ TX_ER/ TXD4 IOPU MII Transmit Error: When driven high, the 4B/5B encode process substitutes the Transmit Error code-group (/H/) for the encoded data word. This input is ignored in 10Base-T operation. MII Transmit Data 4: In Symbol Interface (5B Decoding) mode, this signal becomes the MII Transmit Data 4 line, the MSB of the 5-bit symbol code-group. • This signal is not used in RMII Mode. • This signal is mux’d with nINT • See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 24 for additional information on configuration/strapping options. TX_EN IPD Transmit Enable: Indicates that valid data is presented on the TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0] have valid data. TX_CLK O Transmit Clock: 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. • This signal is not used in RMII Mode. • For proper TXCLK operation, RX_ER and RX_DV must NOT be driven high externally on a hardware reset or on a LAN8700 power up. |
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