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LAN8700i Datasheet(PDF) 40 Page - Microchip Technology |
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LAN8700i Datasheet(HTML) 40 Page - Microchip Technology |
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40 / 74 page  LAN8700/LAN8700i DS00002260A-page 40 2007-2016 Microchip Technology Inc. 5.3 Interrupt Management The Management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register 30. The Interrupt system on the Microchip LAN8700/8700I has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nINT. The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative interrupt mode would need to be setup again after a power-up or hard reset. 5.3.1 PRIMARY INTERRUPT SYSTEM bit The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt System is always selected after power-up or hard reset. 29.1 INT1 1 = Auto-Negotiation Page Received 0 = not source of interrupt RO/ LH X 29.0 Reserved Ignore on read. RO/ LH 0 TABLE 5-44: REGISTER 30 - INTERRUPT MASK Address Name Description Mode Default 30.15:8 Reserved Write as 0; ignore on read. RO 0 30.7:1 Mask Bits 1 = interrupt source is enabled 0 = interrupt source is masked RW 0 30.0 Reserved Write as 0; ignore on read RO 0 TABLE 5-45: REGISTER 31 - PHY SPECIAL CONTROL/STATUS Address Name Description Mode Default 31.15:13 Reserved Write as 0, ignore on read. RW 0 31.12 Autodone Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done Note: This is a duplicate of register 1.5, however reads to register 31 do not clear status bits. RO 0 31.11:10 Reserved Write as 0, ignore on Read. RW XX 31.9:7 Reserved Write as 0, ignore on Read. RW 0 31.6 Enable 4B5B 0 = Bypass encoder/decoder. 1 = enable 4B5B encoding/decoding. MAC Interface must be configured in MII mode. RW 1 31.5 Reserved Write as 0, ignore on Read. RW 0 31.4:2 Speed Indication HCDSPEED value: [001]=10Mbps Half-duplex [101]=10Mbps Full-duplex [010]=100Base-TX Half-duplex [110]=100Base-TX Full-duplex RO XXX 31.1 Reserved Write as 0; ignore on Read RW 0 31.0 Scramble Disable 0 = enable data scrambling 1 = disable data scrambling, RW 0 TABLE 5-43: REGISTER 29 - INTERRUPT SOURCE FLAGS (CONTINUED) Address Name Description Mode Default |
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