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LAN8700i Datasheet(PDF) 38 Page - Microchip Technology |
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LAN8700i Datasheet(HTML) 38 Page - Microchip Technology |
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38 / 74 page  LAN8700/LAN8700i DS00002260A-page 38 2007-2016 Microchip Technology Inc. Note 5-1 The default value of this field is determined by the strapping of the COL/RMII/CRS_DV pin. Refer to Section 4.6.3, "MII vs. RMII Configuration," on page 21 for additional information. 17.10 MDPREBP Management Data Preamble Bypass: 0 – detect SMI packets with Preamble 1 – detect SMI packets without preamble RW 0 17.9 FARLOOPBACK Force the module to the FAR Loop Back mode, i.e. all the received packets are sent back simultaneously (in 100Base-TX only). This bit is only active in RMII mode. In this mode the user needs to supply a 50MHz clock to the PHY. This mode works even if MII Isolate (0.10) is set. RW 0 17.8:7 Reserved Write as 0, ignore on read. RW 00 17.6 ALTINT Alternate Interrupt Mode. 0 = Primary interrupt system enabled (Default). 1 = Alternate interrupt system enabled. See Section 5.3, "Interrupt Management," on page 40. RW 0 17.5:4 Reserved Write as 0, ignore on read. RW 00 17.3 PHYADBP 1 = PHY disregards PHY address in SMI access write. RW 0 17.2 Force Good Link Status 0 = normal operation; 1 = force 100TX- link active; Note: This bit should be set only during lab testing RW 0 17.1 ENERGYON ENERGYON – indicates whether energy is detected on the line (see Section 5.4.5.2, "Energy Detect Power- Down," on page 43); it goes to “0” if no valid energy is detected within 256ms. Reset to “1” by hardware reset, unaffected by SW reset. RO X 17.0 Reserved Write as 0. Ignore on read. RW 0 TABLE 5-39: REGISTER 18 - SPECIAL MODES Address Name Description Mode Default 18.15 Reserved Write as 0, ignore on read. RW 0 18.14 MIIMODE MII Mode: Reflects the mode of the digital interface: 0 – MII interface. 1 – RMII interface Note: When writing to this register, the default value of this bit must always be written back. RW, NASR Note 5-1 18.13:8 Reserved Write as 0, ignore on read. RW, NASR 000000 18.7:5 MODE PHY Mode of operation. Refer to Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46 for more details. RW, NASR XXX EVB8700 default 111 18.4:0 PHYAD PHY Address. The PHY Address is used for the SMI address and for the initialization of the Cipher (Scrambler) key. Refer to Section 5.4.9.1, "Physical Address Bus - PHYAD[4:0]," on page 46 for more details. RW, NASR PHYAD EVB8700 default 11111 TABLE 5-38: REGISTER 17 - MODE CONTROL/STATUS (CONTINUED) Address Name Description Mode Default |
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