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LAN9118 Datasheet(PDF) 7 Page - Microchip Technology |
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LAN9118 Datasheet(HTML) 7 Page - Microchip Technology |
7 / 109 page 2005-2016 Microchip Technology Inc. DS00002266A-page 7 LAN9118 1.4 Receive and Transmit FIFOs The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between the host interface and the MAC through which all transmitted and received data and status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are configurable in size, allowing increased flexibility. 1.5 Interrupt Controller The LAN9118 supports a single programmable interrupt. The programmable nature of this interrupt allows the user the ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval is provided. 1.6 GPIO Interface A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9118. It is accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with program- mable polarity. 1.7 Serial EEPROM Interface A serial EEPROM interface is included in the LAN9118. The serial EEPROM is optional and can be programmed with the LAN9118 MAC address. The LAN9118 can optionally load the MAC address automatically after power-on. 1.8 Power Management Controls The LAN9118 supports comprehensive array of power management modes to allow use in power sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9118. An external PME (Power Management Event) interrupt is provided to indicate detection of a wakeup event. 1.9 General Purpose Timer The general-purpose timer has no dedicated function within the LAN9118 and may be programmed to issue a timed interrupt. 1.10 Host Bus Interface (SRAM Interface) The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the LAN9118 Control and Status Registers (CSR’s). The host bus interface is the primary bus for connection to the embedded host system. This interface models an asyn- chronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are supported. The LAN9118 host bus interface supports 32-bit and 16-bit bus transfers; internally, all data paths are 32-bits wide. The LAN9118 can be interfaced to either Big-Endian or Little-Endian processors in either 32-bit or 16-bit external bus width modes of operation. The host bus data Interface is responsible for host address decoding and data bus steering. The host bus interface han- dles the 16 to 32-bit conversion when the LAN9118 is configured with a 16-bit host interface. Additionally, when Big Endian mode is selected, the data path to the internal controller registers will be reorganized accordingly. |
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Similar Description - LAN9118 |
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