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LAN89218AQR-B Datasheet(PDF) 7 Page - Microchip Technology |
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LAN89218AQR-B Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 148 page  2008-2015 Microchip Technology Inc. DS60001255B-page 7 LAN89218 1.2 Internal Block Overview This section provides an overview of the major functional blocks of the LAN89218, as shown in Figure 1-2. 1.3 10/100 Ethernet PHY The LAN89218 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation. Minimal external components are required for the utilization of the Integrated PHY. 1.4 10/100 Ethernet MAC The transmit and receive data paths are separate within the MAC allowing for the highest performance possible, especially in full duplex mode. The data paths connect to the PIO interface via separate buses to increase performance. Payload data as well as transmit and receive status are passed on these buses. A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the host through the PIO interface function. On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port internal to the LAN89218. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. The MAC Interface Layer (MIL), within the MAC, contains a 2 kByte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission. FIGURE 1-2: INTERNAL BLOCK DIAGRAM 10/100 Ethernet PHY 10/100 Ethernet MAC 2 kB to 14 kB Configurable TX FIFO SRAM I/F Interrupt Controller GP Timer PIO Controller IRQ FIFO_SEL 3.3 V to 1.8 V Core Regulator +3.3 V LAN EEPROM Controller EEPROM (Optional) RX Status FIFO TX Status FIFO MIL - RX Elastic Buffer - 128 bytes PME Wakup Indicator Host Bus Interface (HBI) Power Management 2 kB to 14 kB Configurable RX FIFO MIL - TX Elastic Buffer – 2 kbytes RX Checksum Offload Engine TX Checksum Offload Engine 25 MHz PLL +3.3 V 3.3 V to 1.8 V PLL Regulator |
Similar Part No. - LAN89218AQR-B |
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Similar Description - LAN89218AQR-B |
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