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ICS94201 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS94201 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 18 page 6 ICS94201 Byte 1: Output Control Register (1 = enable, 0 = disable) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default Byte 3: Output Control Register (1 = enable, 0 = disable) Byte 2: Output Control Register (1 = enable, 0 = disable) Byte 4: Output Control Register (1 = enable, 0 = disable) Byte 5: Output Control Register (1 = enable, 0 = disable) Byte 6: Byte Count Read Back Register Note: Writing to this register will configure byte count and how many bytes will be read back, default is 6 bytes. t i B# n i PD W Pn o i t p i r c s e D 7 t i B9 31 7 M A R D S 6 t i B0 41 6 M A R D S 5 t i B2 41 5 M A R D S 4 t i B3 41 4 M A R D S 3 t i B4 41 3 M A R D S 2 t i B6 41 2 M A R D S 1 t i B7 41 1 M A R D S 0 t i B8 41 0 M A R D S t i B# n i PD W Pn o i t p i r c s e D 7 t i B8 1 2 _ 6 6 V 3 6 t i B6 1 0 _ 6 6 V 3 5 t i B7 1 1 _ 6 6 V 3 4 t i B- X # 4 S F 3 t i B4 51 C I P A O I 2 t i B- X # 1 S F 1 t i B1 51 1 K L C U P C 0 t i B2 51 0 K L C U P C t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 0 ) e t o N ( d e v r e s e R 6 t i B- 0 ) e t o N ( d e v r e s e R 5 t i B- 0 ) e t o N ( d e v r e s e R 4 t i B- 0 ) e t o N ( d e v r e s e R 3 t i B- 0 ) e t o N ( d e v r e s e R 2 t i B- 1 ) e t o N ( d e v r e s e R 1 t i B- 1 ) e t o N ( d e v r e s e R 0 t i B- 0 ) e t o N ( d e v r e s e R t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B- 1 ) d e v r e s e R ( 3 t i B6 21 1 1 M A R D S 2 t i B7 21 0 1 M A R D S 1 t i B0 31 9 M A R D S 0 t i B1 31 8 M A R D S t i B# n i PD W Pn o i t p i r c s e D 7 t i B0 21 7 K L C I C P 6 t i B9 11 6 K L C I C P 5 t i B7 11 5 K L C I C P 4 t i B6 11 4 K L C I C P 3 t i B5 11 3 K L C I C P 2 t i B3 11 2 K L C I C P 1 t i B2 11 1 K L C I C P 0 t i B1 11 0 K L C I C P t i B# n i PD W Pn o i t p i r c s e D 7 t i B- X # 3 S F 6 t i B- X # 0 S F 5 t i B- X # 2 S F 4 t i B5 31 z H M 4 2 3 t i B- 1 ) d e v r e s e R ( 2 t i B4 31 z H M 8 4 1 t i B- 1 ) d e v r e s e R ( 0 t i B8 31 F _ M A R D S |
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