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PL904XXX Datasheet(PDF) 4 Page - Micrel Semiconductor

Part # PL904XXX
Description  a small form-factor, high performance, programmable device
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

PL904XXX Datasheet(HTML) 4 Page - Micrel Semiconductor

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Micrel, Inc.
PL904xxx
September 11, 2015
4
Revision 1.0
tcghelp@micrel.com or (408) 955-1690
Functional Description
The PL904xxx series is a very flexible, advanced programmable jitter filter design for high performance, small form-factor
applications. The PL904xxx accepts a reference clock input between 12MHz and 250MHz that can be either differential or
single-ended. The PL904xxx is capable of producing up to 2 differential outputs up to 850MHz. The most common
configuration will be with the same input and output frequency, but this flexible design also allows frequency translation
from one frequency to another frequency, as long as both frequencies are within the specified ranges for input and output.
Jitter Attenuation
Typically, the jitter attenuation settings will be optimized for one particular input and output frequency.
The PL904xxx excels at attenuating deterministic jitter that presents itself as spurs in the phase noise plot above 1MHz.
Output Logic Programming
Available output logic types are LVPECL, LVDS, HCSL,
and LVCMOS.
Each output can be programmed individually to one of the
four logic types.
All logic types are differential, except LVCMOS. For
LVCMOS, only the true channel of the output pair is
enabled and the complementary channel is disabled. With
LVCMOS, there is also an output drive setting. There is
one setting for all LVCMOS outputs, so all LVCMOS
outputs will have the same drive strength.
Unused outputs are disabled to high impedance.
Input Selection
The reference input for the device can be programmed to
be either differential or single ended and requires only a
small amplitude. See Figure 1 and Figure 2.
The single-ended signal can be LVCMOS and the
differential signal can be any of the differential logic types.
For the differential logic types, it is important to use the
appropriate termination for the logic type.
Figure 1. Differential Input Signal
Figure 2. Single-Ended Input Signal


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