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SST39VF402C-70-4C-B3KE Datasheet(PDF) 5 Page - Microchip Technology |
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SST39VF402C-70-4C-B3KE Datasheet(HTML) 5 Page - Microchip Technology |
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5 / 38 page  ©2014 Silicon Storage Technology, Inc. DS20005053B 04/14 5 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Figure 4: Pin Assignments for 48-Ball WFBGA Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 1. AMS = Most significant address AMS =A17 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST39VF401C/402C or 3.0-3.6V for SST39LF401C/402C VSS Ground NC No Connection Unconnected pins. RY/BY# Ready/Busy# To output the status of a Program or Erase operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. T1.2 25053 A2 A1 A0 CE# VSS A4 A3 A5 DQ8 OE# DQ0 A6 A7 NC DQ10 DQ9 DQ1 A17 WP# NC DQ2 NC DQ3 NC VDD WE# DQ12 RST# RY/BY# NC DQ13 A9 A10 A8 DQ4 DQ5 DQ14 A11 A13 A12 DQ11 DQ6 DQ15 A14 A15 A16 DQ7 VSS TOP VIEW (balls facing down) AB C D E F G H J K L 6 5 4 3 2 1 25053 48-wfbga MAQ P3.0 |
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