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5962-9561318HYC Datasheet(PDF) 5 Page - Micross Components |
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5962-9561318HYC Datasheet(HTML) 5 Page - Micross Components |
5 / 12 page SRAM AS5C4009 AS5C4009 Rev. 5.2 01/10 Micross Components reserves the right to change products or specifications without notice. 5 AC TEST CONDITIONS Input pulse levels ................................... Vss to 3.0V Input rise and fall times ....................................... 3ns Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Output load ......................................... See Figures 1 NOTES 1. Overshoot: Vcc +3.0V for pulse width < 20ms. 2. Undershoot: -3V for pulse width < 20ms. 3. I CC is dependent on output loading and cycle rates. 4. This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. At any given temperature and voltage condition, t HZCE is less than t LZCE , and t HZWE is less than t LZWE . 7. WE\ is HIGH for READ cycle. 8. Device is continuously selected. Chip enables and output enables are held in their active state. 9. Address valid prior to, or coincident with, latest occurring chip enable. 10. tRC = Read Cycle Time. 11. Chip enable and write enable can initiate and terminate a WRITE cycle. 12. Output enable (OE\) is inactive (HIGH). 13. Output enable (OE\) is active (LOW). 14. ASI does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150°C. Care should be taken to limit power to acceptable levels. 15. All voltage referenced to Vss (GND). Fig. 1 Output Load Equivalent DATA RETENTION ELECTRICAL CHARACTERISTICS DESCRIPTION SYMBOL MIN MAX UNITS NOTES VCC for Retention Data VDR 2V CE\ > (VCC - 0.2V) VCC = 2V ICCDR 100 μA VIN > (VCC - 0.2V) VCC = 3V ICCDR 200 μA Chip Deselect to Data Retention Time tCDR 0ns 4 Operation Recovery Time tR 5ms 4, 10 Data Retention Current CONDITIONS 167 ohms 1.73V C=30pF Q C = 100pF 50 ohms |
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