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AS4DDR232M72APBGR-5 Datasheet(PDF) 11 Page - Micross Components |
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AS4DDR232M72APBGR-5 Datasheet(HTML) 11 Page - Micross Components |
11 / 28 page iPEM 2.4 Gb SDRAM-DDR2 AS4DDR232M72APBG AS4DDR232M72APBG Rev. 1.1 12/12 11 Micross Components reserves the right to change products or specifications without notice. FIGURE 7 – EXTENDED MODE REGISTER DEFINITION EXTENDED MODE REGISTER (EMR) The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable.These functions are controlled via the bits shown in Figure 7. The EMR is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts areinprogress,andthecontrollermustwaitthespecifiedtime t MRD before initiating any subsequent operation. Violating either oftheserequirementscouldesultinunspecifiedoperation. EXTENDED MODE REGISTER (EMR) The extended mode register controls functions beyond until it is programmed again or the device loses power. those controlled by the mode register; these additional Reprogramming the EMR will not alter the contents of the functions are DLL enable/disable, output drive strength, memory array, provided it is performed correctly. on die termination (ODT) (RTT), posted AL, off-chip driver The EMR must be loaded when all banks are idle and impedance calibration (OCD), DQS# enable/disable, no bursts are in progress, and the controller must wait RDQS/RDQS# enable/disable, and output disable/enable. the specified time tMRD before initiating any subsequent These functions are controlled via the bits shown in operation. Violating either of these requirements could Figure 7. The EMR is programmed via the LOAD MODE result in unspecified operation. (LM) command and will retain the stored information FIGURE 7 – EXTENDED MODE REGISTER DEFINITION DLL out A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended Mode Register (Ex) Address Bus 9 7 6 5 4 3 8 2 1 0 A10 A12 A11 10 11 12 13 02 14 i 0 1 2 3 4 Reserved Reserved Reserved E3 0 1 0 1 0 1 0 1 E4 0 0 1 1 0 0 1 1 E5 0 0 0 0 1 1 1 1 0 1 Enable (Normal) E0 15 0 1 le No E11 OCD Program A13 ODS Rtt 0 1 le Enable Disable E10 Rtt (nominal) Rtt Disabled 75Ω 150Ω 50Ω E2 0 1 0 1 E6 0 0 1 1 0 1 Outputs Enabled Disabled E12 0 1 0 1 ) ) ) ) E15 0 0 1 1 E14 MRS OCD Operation 1 Reserved Reserved Reserved OCD default state 1 E7 0 1 0 0 1 E8 0 0 1 0 1 E9 0 0 0 1 1 0 1 Output Drive E1 Note: 1. During initialization, all three bits must be set to "1" for OCD default state, initialization procedure. 2.. E13 (A13) is not used on this device. then must be set to "0" before initialization is finished, as detailed in the Posted CAS# Rtt BA0 BA1 Posted CAS# Add tive Laten cy (AL) DLL Enable Disable (Test/Debug) RDQS Enab Yes DQS# DQS# Enab RDQS Mo de Register Set Mode Register Set (MRS Extended Mode Register (EMR S Extended Mode Register (EMR S2 Extended Mode Register (EMR S3 OCD Not Supported Strength Full Strength (18 Ω target) Reduced Strength (40 Ω target) AS4DDR232M72PBG 11 AustinSemiconductor, Inc. • (512) 339-1188 • www.austinsemiconductor.com Rev. 0.0 07/06 iPEM 2.4 Gb SDRAM-DDR2 AS4DDR232M72PBG |
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