iPEM

2.4 Gb SDRAM-DDR2

AS4DDR232M72APBG

AS4DDR232M72APBG

Rev. 1.1 12/12

10

Micross Components reserves the right to change products or specifications without notice.

CAS LATENCY (CL)

TheCASlatency(CL)isdefinedbybitsM4-M6,asshown

in Figure 5. CL is the delay, in clock cycles, between the

registrationofaREADcommandandtheavailabilityofthefirst

bit of output data. The CL can be set to 3, 4, 5, or 6 clocks,

depending on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS

additive latency (AL). This feature allows the READ command

internal command to the DDR2 SDRAM by AL clocks.

Examples of CL = 3 and CL = 4 are shown in Figure 6; both

assume AL = 0. If a READ command is registered at clock

edge n, and the CL is m clocks, the data will be available

nominally coincident with clock edge n+m (this assumes

AL = 0).

FIGURE 6 - CAS LATENCY (CL)

CAS LATENCY (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown

in Figure 5. CL is the delay, in clock cycles, between the

registration of a READ command and the availability of

the first bit of output data. The CL can be set to 3, 4, 5,

or 6 clocks, depending on the speed grade option being

used.

DDR2 SDRAM does not support any half-clock latencies.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted

CAS additive latency (AL). This feature allows the READ

internal command to the DDR2 SDRAM by AL clocks.

Examples of CL = 3 and CL = 4 are shown in Figure 6;

both assume AL = 0. If a READ command is registered

at clock edge n, and the CL is m clocks, the data will be

available nominally coincident with clock edge n+m (this

assumes AL = 0).

FIGURE 6 – CAS LATENCY (CL)

T0

T1

T2

T3

T4

T5

T6

CK#

CK

COMMAND

DQS, DQS#

DQ

CK#

CK

COMMAND

DQS, DQS#

DQ

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal tAC, tDQSCK, and tDQSQ

n + 3

n + 2

n + 1

CL = 3 (AL = 0)

READ

NOP

NOP

NOP

n

NOP

NOP

NOP

n + 3

n + 2

n + 1

CL = 4 (AL = 0)

READ

T0

T1

T2

NOP

NOP

NOP

n

T3

T4

T5

NOP

NOP

T6

NOP

TRANSITIONING DATA

DON’T CARE

AS4DDR232M72PBG

10

AustinSemiconductor, Inc. • (512) 339-1188 • www.austinsemiconductor.com

Rev. 0.0

07/06

iPEM

2.4 Gb SDRAM-DDR2

AS4DDR232M72PBG