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IR35203 Datasheet(PDF) 5 Page - International Rectifier

Part # IR35203
Description  61 Dual Output Digital Multi-Phase Controller
Download  56 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IR35203 Datasheet(HTML) 5 Page - International Rectifier

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6+1 Dual Output Digital Multi-Phase Controller
IR35203
www.irf.com | © 2016 International Rectifier
February 8, 2016 | V1.5
5
PIN DESCRIPTIONS
PIN#
PIN NAME
TYPE
PIN DESCRIPTION
1
ISEN6
A [I]
Phase 6 Current Sense Input. Phase 6 sensed current input (+).Short to GND if not used.
2
RCSP
A [O]
Resistor Current Sense Positive. This pin is connected to an external network to set the load
line slope, bandwidth and temperature compensation for Loop 1.
3
RCSM
A [O]
Resistor Current Sense Minus. This pin is connected to an external network to set the load line
slope, bandwidth and temperature compensation for Loop 1.
4
VRDY2
D [O]
Voltage Regulator Ready Output (Loop #2). Open-drain output that asserts high when the VR
has completed soft-start to Loop #2 boot voltage. Pull-up to an external voltage through a
resistor.
5
VSEN
A [I]
Voltage Sense Input. This pin is connected directly to the VR output voltage of Loop #1 at the
load and should be routed differentially with VRTN.
6
VRTN
A [I]
Voltage Sense Return Input. This pin is connected directly to Loop#1 ground at the load and
should be routed differentially with VSEN.
7
I_IN
A [I]
I in. Input current signal that ranges from 0 to 1.25Vdc indicating a maximum input current of
62.5 Amps.
8
TSEN1
A [I]
Temperature Sense Input Loop 1. An NTC network or the temperature reporting output from an
IR PowIRstage can be connected to this pin to measure temperature for VRHOT and OTP
shutdown. When connected to the IR PowIRstage’s temperature output; the scaled input voltage
to the controller needs to be at a gain of 4.88mV per degC and an offset of 0.365 Vdc so the
controller can correctly report temperature. Typically a 10kohm and 6.49kohm resistive divider is
used to accomplish the scaling between the power stage and the controller.
9
CFILT
A [O]
1.8V Decoupling. A 1
F capacitor on this pin provides decoupling for the internal 1.8V supply.
10
VRDY1
D [O]
Voltage Regulator Ready Output (Loop #1). Open-drain output that asserts high when the VR
has completed soft-start to Loop #1 boot voltage. Pull-up to an external voltage through a
resistor.
11
EN_L2
CAT_FLT
D[I]
D[O]
Enable Input for Loop #2. This pin may be configured as an Enable input for loop #2.
Catastrophic Fault Output Pin. This pin may be used as a Catastrophic Fault CMOS Output Pin
that is driven to VCC under output OVP, NVM CRC errors or a TSEN fault input.
12
VINSEN
A [I]
Voltage Sense Input. This is used to detect and measure a valid input supply voltage (typically
4.5V-13.2V) to the VR.
13
PIN_ALERT#
D [O]
PIN_ALERT# Output. Active low alert pin that can be programmed to assert if the input power
exceeds user-defined threshold. Pull-up to an external voltage through a resistor.
14
SV_ALERT#
D [O]
Serial VID ALERT# (INTEL). SVID ALERT# is pulled low by the controller to alert the CPU of
new VR12/12.5 Status. Pull-up to an external voltage through a resistor.
15
SV_CLK
D [I]
Serial VID Clock Input. Clock input driven by the CPU Master.
16
SV_DIO
D [B]
Serial VID Data I/O. Is a bi-directional serial line over which the CPU Master issues commands to
slave/s and receives data back.
17
VRHOT_ICRIT#
D [O]
VRHOT_ICRIT# Output. Active low alert pin that can be programmed to assert if temperature or
average load current exceeds user-definable thresholds. Pull-up to an external voltage through a
resistor.
18
EN
D [I]
VR Enable Input. ENABLE is used to power-on the regulator, provided Vin and Vcc are present.
ENABLE is not pulled up in the controller. The polarity of the chip enable function is bit-settable to
either an active high or an active low configuration. When the controller is disabled, the controller
de-asserts VR READY and shuts down the regulator. ENABLE pin cannot be left
floating. ENABLE pin must be pulled high or low.
19
ADDR_PROT
D [B]/
Bus Address & I2C Bus Protection. A resistor to ground on this pin sets the offset to the NVM
value of the I2C address if configured to do so. Subsequently, this pin becomes a logic input to
enable or disable communication on the I2C bus when protection is enabled. Requires a 0.01µF
to ground for noise filtering.
20
SM_ALERT#
D [O]
SMBus/PMBus Alert Line. Active low alert pin to indicate that the regulator status has changed.
Requires a pull-up. Ground if not used.


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