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CDP6402CD Datasheet(PDF) 11 Page - Harris Corporation |
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CDP6402CD Datasheet(HTML) 11 Page - Harris Corporation |
11 / 12 page 5-84 NOTES: 1. The holding register is loaded on the trailing edge of TBRL. 2. The transmitter shift register, if empty , is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC after the trailing edge of TBRL and transmission of a start bit occurs 1/2 clock period + tCD later. FIGURE 7. TRANSMITTER TIMING WAVEFORMS TRC TBRL TRO TBRE TRE T BUS 0 T BUS 7 tCC tCL tCH tTHC 12 tTHTH tCD tCT tTTS tTTHR tDT tDT DATA tCD 1ST DATA BIT TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) TRANSMITTER BUFFER REGISTER LOADED (NOTE 1) 34 56 7 14 15 16 1 23 NOTES: 1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. The start bit may be completely asynchronous with the clock. 2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true.. FIGURE 8. RECEIVER TIMING WAVEFORMS RRC R BUS 7 DR DRR tCC tCL tCH tDC 12 START BIT PARITY tDDA tCDV CLOCK 7 1/2 SAMPLE 34 56 7 16 (NOTE 1) RRI 12 34 56 78 9 STOP BIT 1 CLOCK 7 1/2 LOAD HOLDING REGISTER DATA tCDA tDD tCOE tCPE tCFE R BUS 0 - OE PE (NOTE 2) FE CDP6402, CDP6402C |
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