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STM8AL31E89 Datasheet(PDF) 2 Page - STMicroelectronics

Part # STM8AL31E89
Description  device limitations
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8AL31E89 Datasheet(HTML) 2 Page - STMicroelectronics

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Contents
STM8AL3xxx STM8L052R8 STM8L1xxx6/8
2/18
DocID17922 Rev 6
Contents
1
Silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Core limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1
Interrupt service routine (ISR) executed with priority of main process . . 6
1.1.2
Main CPU execution is not resumed after an ISR resets the AL bit . . . . 6
1.1.3
Unexpected DIV/DIVW instruction result in ISR . . . . . . . . . . . . . . . . . . . 6
1.1.4
Incorrect code execution when WFE execution is interrupted by ISR
or event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5
Core kept in stall mode when DMA transfer occurs during program/
erase operation to EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.6
Incorrect code execution when FLASH/EEPROM memory wakes up
from power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.2.1
Default DAC output level when output buffer is enabled . . . . . . . . . . . . 11
1.2.2
32.768 kHz LSE crystal accuracy may be disturbed by the use of
adjacent I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.3
RTC LSE failure can be detected just once after power-on reset . . . . . 11
1.3
Peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.1
SPI2 peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.2
I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.3
USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.4
Timer limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17


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