 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PCA9655E Datasheet(PDF) 10 Page - ON Semiconductor |
|
||||||||||||||||||||||||||||||
PCA9655E Datasheet(HTML) 10 Page - ON Semiconductor |
|
|
10 / 20 page  PCA9655E www.onsemi.com 10 Registers 4 and 5: Polarity Inversion Registers These registers allow the polarity of the data in the input port registers to be inverted. The input port data polarity will be inverted when its corresponding bit in these registers is set (written with ‘1’), and retained when the bit is cleared (written with a ‘0’). Table 12. POLARITY INVERSION PORT 0 REGISTER Bit 7 6 5 4 3 2 1 0 Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0 Default 0 0 0 0 0 0 0 0 Table 13. POLARITY INVERSION PORT 1 REGISTER Bit 7 6 5 4 3 2 1 0 Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 Default 0 0 0 0 0 0 0 0 Registers 6 and 7: Configuration Registers The I/O pin directions are configured through the configuration registers. When a bit in the configuration registers is set (written with ‘1’), the bit’s corresponding port pin is enabled as an input with the output driver in high−impedance. When a bit is cleared (written with ‘0’), the corresponding port pin is enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At reset, the device’s ports are inputs with a pull−up to VDD. Table 14. CONFIGURATION PORT 0 REGISTER Bit 7 6 5 4 3 2 1 0 Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0 Default 1 1 1 1 1 1 1 1 Table 15. CONFIGURATION PORT 1 REGISTER Bit 7 6 5 4 3 2 1 0 Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 Default 1 1 1 1 1 1 1 1 Power−on Reset Upon application of power, an internal Power−On Reset (POR) holds the PCA9655E in a reset condition while VDD is ramping up. When VDD has reached VPOR, the reset condition is released and the PCA9655E registers and SMBus state machine will initialize to their default states. The reset is typically completed by the POR and the part enabled by the time the power supply is above VPOR. However, when doing a power reset cycle, it is necessary to lower the power supply below 0.2 V, and then restored to the operating voltage. Please refer to application note AND9169/D for recommended power−up and power−cycle reset profiles. I/O Port (see Figure 2) When an I/O pin is configured as an input, FETs Q1 and Q2 are off, creating a high−impedance input with a weak pull−up (100 k W typ) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. When the I/O pin is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low−impedance path that exists between the pin and either VDD or VSS. |
Similar Part No. - PCA9655E |
|
Similar Description - PCA9655E |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
