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LDES250UF6S Datasheet(PDF) 8 Page - Sensortechnics GmbH

Part # LDES250UF6S
Description  Digital low differential pressure sensors
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Manufacturer  SENSORTECHNICS [Sensortechnics GmbH]
Direct Link  http://www.sensortechnics.com
Logo SENSORTECHNICS - Sensortechnics GmbH

LDES250UF6S Datasheet(HTML) 8 Page - Sensortechnics GmbH

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LDE Series
Digital low differential pressure sensors
www.first-sensor.com
www.sensortechnics.com
Fig. 3: Resistors at both ends of the SPI lines
SPI - SERIAL PERIPHERAL INTERFACE
Introduction
The LDE serial interface is a high-speed synchronous
data input and output communication port. The serial
interface operates using a standard 4-wire SPI bus.
The LDE device runs in SPI mode 0, which requires the
clock line SCLK to idle low (CPOL = 0), and for data to
be sampled on the leading clock edge (CPHA = 0).
Figure 5 illustrates this mode of operation.
Care should be taken to ensure that the sensor is
properly connected to the master microcontroller.
Refer to the manufacturer's datasheet for more
information regarding physical connections.
Application circuit
The use of pull-up resistors is generally unnecessary
for SPI as most master devices are configured for
push-pull mode. If pull-up resistors are required for
use with 3 V LDE devices, however, they should be
greater than 50 k
Ω.
Note: It is important to adhere to the communication protocol in order to avoid damage to the sensor.
There are, however, some cases where it may be
helpful to use 33
Ω series resistors at both ends of the
SPI lines, as shown in Figure 3. Signal quality may be
further improved by the addition of a buffer as shown in
Figure 4. These cases include multiple slave devices
on the same bus segment, using a master device
with limited driving capability and long SPI bus lines.
If these series resistors are used, they must be
physically placed as close as possible to the pins of
the master and slave devices.
Signal control
The serial interface is enabled by asserting /CS low.
The serial input clock, SCLK, is gated internally to
begin accepting the input data at MOSI, or sending
the output data on MISO. When /CS rises, the data
clocked into MOSI is loaded into an internal register.
Fig. 4: Addition of a buffer
SCLK
MOSI
MISO
/CS
SCLK
MOSI
MISO
/CS
Sensor
33
33
33
33
33
33
33
33
SCLK
MOSI
MISO
/CS
SCLK
MOSI
MISO
/CS
Sensor
33
33
33
33
33
33
33
33
33
33
33
33
/OE
/OE
/OE
/OE


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