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LM2792LDX-L Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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LM2792LDX-L Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 10 page Application Information (Continued) important to have good thermal conduction with a proper layout to reduce thermal resistance. POWER EFFICIENCY An ideal power efficiency for a voltage doubler switched capacitor converter is given as the output voltage of the doubler over twice the input voltage as follows: Efficiency = (V DIODE*IDIODE)/(VIN *IDIODE* Gain) = V DIODE /2VIN In the case of the LM2792, a more accurate efficiency cal- culation can be applied as the given formula below. Efficiency = ((V D1*ID1)+(VD2*ID2))/(ISUPPLY*VIN) It is clear that the efficiency will depend on the supply voltage in the above equation. As such, the lower the supply voltage, the higher the efficiency. POWER DISSIPATION The maximum allowable power dissipation that this package is capable of handling can be determined as follows: P DMax =(TJMax -TA)/ θ JA where T JMax is the maximum junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance of the specified package. The actual power dissipation of the device can be calculated using this equation: P Dissipation = (2VIN -VDIODE)*ILOAD As an example, if V IN in the target application is 4.2V, VDIODE = 3.0V and worse case current consumption is 32mA (17mA for each diode). P Dissipation = ((2*4.2) -3.0)*0.032 = 173mW Power dissipation must be less than that allowed by the package. Please refer to the Absolute Maximum Rating of the LM2792. PCB LAYOUT CONSIDERATIONS The LLP is a leadframe based Chip Scale Package (CSP) with very good thermal properties. This package has an exposed DAP (die attach pad) at the center of the package measuring 2.0mm x 1.2mm. The main advantage of this exposed DAP is to offer lower thermal resistance when it is soldered to the thermal land on the PCB. For PCB layout, National highly recommends a 1:1 ratio between the pack- age and the PCB thermal land. To further enhance thermal conductivity, the PCB thermal land may include vias to a ground plane. For more detailed instructions on mounting LLP packages, please refer to National Semiconductor Ap- plication Note AN-1187. www.national.com 9 |
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